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Message-ID: <20171113103758.GA29311@dazhang1-ssd.sh.intel.com>
Date: Mon, 13 Nov 2017 18:37:59 +0800
From: Yi Zhang <yi.z.zhang@...ux.intel.com>
To: Paolo Bonzini <pbonzini@...hat.com>
Cc: kvm@...r.kernel.org, linux-kernel@...r.kernel.org,
rkrcmar@...hat.com, ravi.sahita@...el.com
Subject: Re: [PATCH RFC 00/10] Intel EPT-Based Sub-page Write Protection
Support.
On 2017-11-10 at 16:39:27 +0100, Paolo Bonzini wrote:
> On 04/11/2017 17:54, Paolo Bonzini wrote:
> > On 04/11/2017 01:12, Yi Zhang wrote:
> >>>
> >> Adding Ravi,
> >>
> >> Does anyone have further comments on current implementation, it is a
> >> important feature in our next generation chip-set.
> >
> > What matters is not the feature, but the use case; without a use case,
> > there is no point in including code for SPP in KVM. KVM doesn't use
> > VMFUNC or #VE for example, because they are not necessary.
> >
> > SPP may become useful once we have the introspection interface. Or, if
> > another hypervisor uses it, support for nested SPP may be useful (for
> > example we support nested VMFUNC and should get nested #VE sooner or
> > later, even though the features are not used on bare metal).
> >
> > Right now, however, supporting SPP does not seem to be particularly
> > important honestly.
>
> Hi Yi Zhang,
>
> are you going to work on nested SPP? I guess that would be most useful
> way to add SPP support to KVM (and you could also test it with
> kvm-unit-tests).
Hi Paolo,
We Haven't planing on the nested support yet, so far there are many hardware
assistance work on current SPP implemetation, and apply it in next
generration icelake chip-set.
Regards
Yi.
>
> Thanks,
>
> Paolo
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