linux-kernel - Re: [RFC 4/7] x86/asm: Fix assumptions that the HW TSS is at the beginning of cpu

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Message-ID: <2fdf9cf9-ec48-e63f-2ec8-44160c206c9a@intel.com>
Date:   Mon, 13 Nov 2017 09:01:26 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     Andy Lutomirski <luto@...nel.org>, X86 ML <x86@...nel.org>
Cc:     Borislav Petkov <bpetkov@...e.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Brian Gerst <brgerst@...il.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [RFC 4/7] x86/asm: Fix assumptions that the HW TSS is at the
 beginning of cpu_tss

On 11/10/2017 08:05 PM, Andy Lutomirski wrote:
> -struct tss_struct doublefault_tss __cacheline_aligned = {
> -	.x86_tss = {
> -		.sp0		= STACK_START,
> -		.ss0		= __KERNEL_DS,
> -		.ldt		= 0,
...
> +struct x86_hw_tss doublefault_tss __cacheline_aligned = {
> +	.sp0		= STACK_START,
> +	.ss0		= __KERNEL_DS,
> +	.ldt		= 0,
> +	.io_bitmap_base	= INVALID_IO_BITMAP_OFFSET,

FWIW, I really like the trend of renaming the hardware structures in
such a way that it's clear that they *are* hardware structures.

It might also be nice to reference the relevant SDM sections on the
topic, or even to include a comment along the lines of how it get used.
This chunk from the SDM is particularly relevant:

"The TSS holds information important to 64-bit mode and that is not
directly related to the task-switch mechanism."