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Message-ID: <mhng-1ea3f488-332b-49dd-a32e-8c97c8caa4b2@palmer-si-x1c4>
Date: Mon, 13 Nov 2017 13:56:22 -0800 (PST)
From: Palmer Dabbelt <palmer@...belt.com>
To: Linus Torvalds <torvalds@...ux-foundation.org>
CC: linux-kernel@...r.kernel.org, patches@...ups.riscv.org,
Arnd Bergmann <arnd@...db.de>, Olof Johansson <olof@...om.net>
Subject: [GIT PULL] RISC-V Port for Linux 4.15 v9
The following changes since commit bebc6082da0a9f5d47a1ea2edc099bf671058bd4:
Linux 4.14 (2017-11-12 10:46:13 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/palmer/linux.git tags/riscv-for-linus-4.15-arch-v9
for you to fetch changes up to 512d88db5ef3de56f392f761657c2ab2cadc0498:
Merge tag 'v4.14' into for-linus (2017-11-13 13:17:51 -0800)
----------------------------------------------------------------
RISC-V Port for Linux 4.15 v9
This tag contains the core RISC-V Linux port, which has been through
nine rounds of review on various mailing lists. The port is not
complete: there's some cleanup patches moving through the review
process, a whole bunch of drivers that need some work, and a lot of
feature additions that will be needed.
The patches contained in this tag have been through nine rounds of
review on the various mailing lists. I have some outstanding cleanup
patches, but since there's been so much review on these patches I
thought it would be best to submit them as-is and then submit explicit
cleanup patches so everyone can review them. This first patch set is
big enough that it's a bit of a pain to constantly rewrite, and it's
caused a few headaches with various contributors.
The port is definately a work in progress. While what's there builds
and boots with 4.14, it's a bit hard to actually see anything happen
because there are no device drivers yet. I maintain a staging branch
that contains all the device drivers and cleanup that actually works,
but those patches won't all be ready for a while. I'd like to get what
we currently have into your tree so everyone can start working from a
single base -- of particular importance is allowing the glibc
upstreaming process to proceed so we can sort out any possibly lingering
user-visible ABI problems we might have.
Copied below is the ChangeLog that contains the history of this patch
set:
(v9) As per suggestions on our v8 patch set, I've split the core architecture code
out from our drivers and would like to submit this patch set to be included
into linux-next, with the goal being to be merged in during the next merge
window. This patch set is based on 4.14-rc2, but if it's better to have it
based on something else then I can change it around.
This patch set contains just the core arch code for RISC-V, so while it builds
an nominally boots, you can't print or take an interrupt so it's not that
useful. If you're looking to actually boot a system it would probably be
better to use the full patch set listed below.
We've collected a handful of tags from reviewers, and the remainder of the
patch set only got minimal feedback last time. Here's what changed:
* We now use the device tree to initialize the timer driver so it's less
tighly coupled with the arch port.
* I cleaned up the defconfigs -- there's actually now just one, and it's
empty. For now I think we're OK with what the kernel sets as defaults, but
I anticipate we'll begin to expand this as people start to use the port
more.
* The VDSO symbols version is sane.
* We WFI while spinning in the boot loop.
* A handful of comments have been added.
While there are still a handful of FIXMEs in this patch set, we've started to
get enough interest from various users and contributors that maintaining an out
of tree patch set is starting to become a big burden. Hopefully the patches
are good enough to merge now, which will at least get everyone working in a
more reasonable manner as we clean up the remaining issues.
This patch set is also availiable on github
https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v9-arch
as is the entire patch set necessary to get a more functional RISC-V system up
and running, including a handful of patches that aren't ready for upstream yet.
https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v9
Hopefully I've managed to get everyone's feedback
Here's the change highlights from the whole patch set:
(v8) I know it may not be the ideal time to submit a patch set right now, as
it's the middle of the merge window, but things have calmed down quite a bit in
the last month so I thought it would be good to get everyone on the same page.
There's been a handful of changes since the last patch set, but most of them
are fairly minor:
* We changed PAGE_OFFSET to allowing mapping more physical memory on 64-bit
systems. This is user configurable, as it triggers a different code model
that generates slightly less efficient code.
* The device tree binding documentation is back, I'd managed to lose it at some
point.
* We now pass the atomic64 test suite. The SBI timer driver has been
* refactored.
(v7) It's been a while since my last patch set, but the changes han been fairly
minimal:
* The PCI cleanup patches have been dropped, we'll do them as a separate patch
set later.
* We've the Kconfig entries from CONFIG_ISA_* to CONFIG_RISCV_ISA_*, to make
grep easier.
* There have been a handful of memory model related tweaks in I/O land,
particularly relating the PCI and the upcoming platform specification.
There are significant comments in the relevant files. This is still a WIP,
but I think we're close to getting as good as we're going to get until we
end up with some more specifications.
(v6) As it's been only a day since the v5 patch set, the changes are pretty
minimal:
* The patch set is now based on linux-next/master, which I believe is a better
base now that we're getting closer to upstream.
* EARLY_PRINTK is no longer an option. Since the SBI console is reasonable,
there's no penalty to enabling it (and thus no benefit to disabling it).
* The mmap syscalls were refactored a bit.
(v5) Things have really started to calm down, so this is fairly similar to the
v4 patch set. The most interesting changes include:
* We've moved back to a single patch set.
* SMP support has been fixed, I was accidentally running on a non-SMP
configuration. There were various mistakes all over the tree as a result of
this.
* The cmpxchg syscalls have been removed, as they were deemed a bad idea. As
a result, RISC-V Linux systems mandate the A extension. The corresponding
Kconfig entry to enable builds on non-A systems has been removed.
* A few more atomic fixes: mostly fence changes, but those resulted in a
handful of additional macros that were no longer necessary.
* riscv_early_sie has been removed.
(v4) There have only been a few changes since the v3 patch set:
* The cmpxchg64 syscall is no longer enabled on 32-bit systems. It's not
possible to provide this on SMP systems, and it's not necessary as glibc
knows not to call it.
* We provide a ELF_HWCAP so users can determine the ISA of the machine the
kernel is running on.
* The multi-line comments are in a better form.
* There were a handful of headers that could be replaced with the asm-generic
versions, and a few unnecessary definitions.
* We no longer use printk, but instead use pr_*.
* A few Kconfig and defconfig entries have been cleaned up.
(v3) A highlight of the changes since the v2 patch set includes:
* We've split out all our drivers into separate patch sets, which I've already
sent out to the relevant maintainers. I haven't included those patches in
this patch set, but some of them are necessary to build our port. A git
tree that contains all our patch sets merged together lives at
<https://github.com/riscv/riscv-linux/tree/riscv-for-submission-v3>.
* The patch set is now split up differently: rather than being split per
directory it is split per topic. Hopefully this will make it easier to
review the port on the mailing list. The split is a bit rough, so you
probably still want to look at the patch set as a whole.
* atomic.h has been completely rewritten and is hopefully now correct. I've
attempted to sanitize the various other memory model related code as well,
and I think it should all be sane now aside from a handful of FIXMEs
commented in the code.
* We've changed the cmpexchg syscall to always exist and to not be
multiplexed. There is also a VDSO entry for compare and exchange, which
allows kernels with the A extension to execute user code without the A
extension reasonably fast.
* Our user-visible register state now contains enough space for the Q
extension for 128-bit floating point, as well as a few words to allow
extensibility to future ISA extensions like the eventual V extension for
vectors.
* A handful of driver cleanups, but these have been split into separate patch
sets now so I won't duplicate them here.
(v2) A highlight of the changes since the v1 patch set includes:
* We've split out our drivers into the right places, which means now there's
a lot more patches. I'll be submitting these patches to various subsystem
maintainers and including them in any future RISC-V patch sets until
they've been merged.
* The SBI console driver has been completely rewritten to use the HVC helpers
and is now significantly smaller.
* We've begun to use weaker barriers as opposed to just the big "fence".
There's still some work to do here, specifically:
- We need fences in the relaxed MMIO functions.
- The non-relaxed MMIO functions are missing R/W bits on their fences.
- Many AMOs need the aq and rl bits set.
* We now have thread_info in task_struct. As a result, sscratch now contains
TP instead of SP. This was necessary because thread_info is no longer on
the stack.
* A few shared routines have been added that we use instead of creating
another arch copy.
----------------------------------------------------------------
Jonathan Neuschäfer (1):
MAINTAINERS: Add RISC-V
Palmer Dabbelt (12):
lib: Add shared copies of some GCC library routines
dt-bindings: RISC-V CPU Bindings
RISC-V: Init and Halt Code
RISC-V: Atomic and Locking Code
RISC-V: Generic library routines and assembly
RISC-V: ELF and module implementation
RISC-V: Task implementation
RISC-V: Device, timer, IRQs, and the SBI
RISC-V: Paging and MMU
RISC-V: User-facing API
RISC-V: Build Infrastructure
Merge tag 'v4.14' into for-linus
Documentation/devicetree/bindings/riscv/cpus.txt | 162 +++++++
MAINTAINERS | 10 +
Makefile | 3 +-
arch/riscv/Kconfig | 310 ++++++++++++++
arch/riscv/Makefile | 72 ++++
arch/riscv/configs/defconfig | 0
arch/riscv/include/asm/Kbuild | 61 +++
arch/riscv/include/asm/asm-offsets.h | 1 +
arch/riscv/include/asm/asm.h | 76 ++++
arch/riscv/include/asm/atomic.h | 375 +++++++++++++++++
arch/riscv/include/asm/barrier.h | 68 +++
arch/riscv/include/asm/bitops.h | 218 ++++++++++
arch/riscv/include/asm/bug.h | 88 ++++
arch/riscv/include/asm/cache.h | 22 +
arch/riscv/include/asm/cacheflush.h | 39 ++
arch/riscv/include/asm/cmpxchg.h | 134 ++++++
arch/riscv/include/asm/compat.h | 29 ++
arch/riscv/include/asm/csr.h | 132 ++++++
arch/riscv/include/asm/current.h | 45 ++
arch/riscv/include/asm/delay.h | 28 ++
arch/riscv/include/asm/dma-mapping.h | 38 ++
arch/riscv/include/asm/elf.h | 84 ++++
arch/riscv/include/asm/hwcap.h | 37 ++
arch/riscv/include/asm/io.h | 303 +++++++++++++
arch/riscv/include/asm/irq.h | 28 ++
arch/riscv/include/asm/irqflags.h | 63 +++
arch/riscv/include/asm/kprobes.h | 22 +
arch/riscv/include/asm/linkage.h | 20 +
arch/riscv/include/asm/mmu.h | 26 ++
arch/riscv/include/asm/mmu_context.h | 69 +++
arch/riscv/include/asm/page.h | 130 ++++++
arch/riscv/include/asm/pci.h | 48 +++
arch/riscv/include/asm/pgalloc.h | 124 ++++++
arch/riscv/include/asm/pgtable-32.h | 25 ++
arch/riscv/include/asm/pgtable-64.h | 84 ++++
arch/riscv/include/asm/pgtable-bits.h | 48 +++
arch/riscv/include/asm/pgtable.h | 430 +++++++++++++++++++
arch/riscv/include/asm/processor.h | 97 +++++
arch/riscv/include/asm/ptrace.h | 118 ++++++
arch/riscv/include/asm/sbi.h | 100 +++++
arch/riscv/include/asm/smp.h | 52 +++
arch/riscv/include/asm/spinlock.h | 165 ++++++++
arch/riscv/include/asm/spinlock_types.h | 33 ++
arch/riscv/include/asm/string.h | 26 ++
arch/riscv/include/asm/switch_to.h | 69 +++
arch/riscv/include/asm/syscall.h | 102 +++++
arch/riscv/include/asm/thread_info.h | 94 +++++
arch/riscv/include/asm/timex.h | 59 +++
arch/riscv/include/asm/tlb.h | 24 ++
arch/riscv/include/asm/tlbflush.h | 64 +++
arch/riscv/include/asm/uaccess.h | 513 +++++++++++++++++++++++
arch/riscv/include/asm/unistd.h | 16 +
arch/riscv/include/asm/vdso.h | 41 ++
arch/riscv/include/asm/word-at-a-time.h | 55 +++
arch/riscv/include/uapi/asm/Kbuild | 27 ++
arch/riscv/include/uapi/asm/auxvec.h | 24 ++
arch/riscv/include/uapi/asm/bitsperlong.h | 25 ++
arch/riscv/include/uapi/asm/byteorder.h | 23 +
arch/riscv/include/uapi/asm/elf.h | 83 ++++
arch/riscv/include/uapi/asm/hwcap.h | 36 ++
arch/riscv/include/uapi/asm/ptrace.h | 90 ++++
arch/riscv/include/uapi/asm/sigcontext.h | 30 ++
arch/riscv/include/uapi/asm/siginfo.h | 24 ++
arch/riscv/include/uapi/asm/ucontext.h | 45 ++
arch/riscv/kernel/.gitignore | 1 +
arch/riscv/kernel/Makefile | 33 ++
arch/riscv/kernel/asm-offsets.c | 322 ++++++++++++++
arch/riscv/kernel/cacheinfo.c | 105 +++++
arch/riscv/kernel/cpu.c | 108 +++++
arch/riscv/kernel/cpufeature.c | 61 +++
arch/riscv/kernel/entry.S | 464 ++++++++++++++++++++
arch/riscv/kernel/head.S | 157 +++++++
arch/riscv/kernel/irq.c | 39 ++
arch/riscv/kernel/module.c | 217 ++++++++++
arch/riscv/kernel/process.c | 129 ++++++
arch/riscv/kernel/ptrace.c | 125 ++++++
arch/riscv/kernel/reset.c | 36 ++
arch/riscv/kernel/riscv_ksyms.c | 15 +
arch/riscv/kernel/setup.c | 257 ++++++++++++
arch/riscv/kernel/signal.c | 292 +++++++++++++
arch/riscv/kernel/smp.c | 110 +++++
arch/riscv/kernel/smpboot.c | 114 +++++
arch/riscv/kernel/stacktrace.c | 177 ++++++++
arch/riscv/kernel/sys_riscv.c | 49 +++
arch/riscv/kernel/syscall_table.c | 25 ++
arch/riscv/kernel/time.c | 61 +++
arch/riscv/kernel/traps.c | 180 ++++++++
arch/riscv/kernel/vdso.c | 125 ++++++
arch/riscv/kernel/vdso/.gitignore | 2 +
arch/riscv/kernel/vdso/Makefile | 63 +++
arch/riscv/kernel/vdso/rt_sigreturn.S | 24 ++
arch/riscv/kernel/vdso/vdso.S | 27 ++
arch/riscv/kernel/vdso/vdso.lds.S | 77 ++++
arch/riscv/kernel/vmlinux.lds.S | 92 ++++
arch/riscv/lib/Makefile | 6 +
arch/riscv/lib/delay.c | 110 +++++
arch/riscv/lib/memcpy.S | 115 +++++
arch/riscv/lib/memset.S | 120 ++++++
arch/riscv/lib/uaccess.S | 117 ++++++
arch/riscv/lib/udivdi3.S | 38 ++
arch/riscv/mm/Makefile | 4 +
arch/riscv/mm/extable.c | 37 ++
arch/riscv/mm/fault.c | 282 +++++++++++++
arch/riscv/mm/init.c | 70 ++++
arch/riscv/mm/ioremap.c | 92 ++++
include/lib/libgcc.h | 43 ++
lib/Kconfig | 18 +
lib/Makefile | 8 +
lib/ashldi3.c | 44 ++
lib/ashrdi3.c | 46 ++
lib/cmpdi2.c | 42 ++
lib/lshrdi3.c | 45 ++
lib/muldi3.c | 72 ++++
lib/ucmpdi2.c | 35 ++
114 files changed, 10317 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/riscv/cpus.txt
create mode 100644 arch/riscv/Kconfig
create mode 100644 arch/riscv/Makefile
create mode 100644 arch/riscv/configs/defconfig
create mode 100644 arch/riscv/include/asm/Kbuild
create mode 100644 arch/riscv/include/asm/asm-offsets.h
create mode 100644 arch/riscv/include/asm/asm.h
create mode 100644 arch/riscv/include/asm/atomic.h
create mode 100644 arch/riscv/include/asm/barrier.h
create mode 100644 arch/riscv/include/asm/bitops.h
create mode 100644 arch/riscv/include/asm/bug.h
create mode 100644 arch/riscv/include/asm/cache.h
create mode 100644 arch/riscv/include/asm/cacheflush.h
create mode 100644 arch/riscv/include/asm/cmpxchg.h
create mode 100644 arch/riscv/include/asm/compat.h
create mode 100644 arch/riscv/include/asm/csr.h
create mode 100644 arch/riscv/include/asm/current.h
create mode 100644 arch/riscv/include/asm/delay.h
create mode 100644 arch/riscv/include/asm/dma-mapping.h
create mode 100644 arch/riscv/include/asm/elf.h
create mode 100644 arch/riscv/include/asm/hwcap.h
create mode 100644 arch/riscv/include/asm/io.h
create mode 100644 arch/riscv/include/asm/irq.h
create mode 100644 arch/riscv/include/asm/irqflags.h
create mode 100644 arch/riscv/include/asm/kprobes.h
create mode 100644 arch/riscv/include/asm/linkage.h
create mode 100644 arch/riscv/include/asm/mmu.h
create mode 100644 arch/riscv/include/asm/mmu_context.h
create mode 100644 arch/riscv/include/asm/page.h
create mode 100644 arch/riscv/include/asm/pci.h
create mode 100644 arch/riscv/include/asm/pgalloc.h
create mode 100644 arch/riscv/include/asm/pgtable-32.h
create mode 100644 arch/riscv/include/asm/pgtable-64.h
create mode 100644 arch/riscv/include/asm/pgtable-bits.h
create mode 100644 arch/riscv/include/asm/pgtable.h
create mode 100644 arch/riscv/include/asm/processor.h
create mode 100644 arch/riscv/include/asm/ptrace.h
create mode 100644 arch/riscv/include/asm/sbi.h
create mode 100644 arch/riscv/include/asm/smp.h
create mode 100644 arch/riscv/include/asm/spinlock.h
create mode 100644 arch/riscv/include/asm/spinlock_types.h
create mode 100644 arch/riscv/include/asm/string.h
create mode 100644 arch/riscv/include/asm/switch_to.h
create mode 100644 arch/riscv/include/asm/syscall.h
create mode 100644 arch/riscv/include/asm/thread_info.h
create mode 100644 arch/riscv/include/asm/timex.h
create mode 100644 arch/riscv/include/asm/tlb.h
create mode 100644 arch/riscv/include/asm/tlbflush.h
create mode 100644 arch/riscv/include/asm/uaccess.h
create mode 100644 arch/riscv/include/asm/unistd.h
create mode 100644 arch/riscv/include/asm/vdso.h
create mode 100644 arch/riscv/include/asm/word-at-a-time.h
create mode 100644 arch/riscv/include/uapi/asm/Kbuild
create mode 100644 arch/riscv/include/uapi/asm/auxvec.h
create mode 100644 arch/riscv/include/uapi/asm/bitsperlong.h
create mode 100644 arch/riscv/include/uapi/asm/byteorder.h
create mode 100644 arch/riscv/include/uapi/asm/elf.h
create mode 100644 arch/riscv/include/uapi/asm/hwcap.h
create mode 100644 arch/riscv/include/uapi/asm/ptrace.h
create mode 100644 arch/riscv/include/uapi/asm/sigcontext.h
create mode 100644 arch/riscv/include/uapi/asm/siginfo.h
create mode 100644 arch/riscv/include/uapi/asm/ucontext.h
create mode 100644 arch/riscv/kernel/.gitignore
create mode 100644 arch/riscv/kernel/Makefile
create mode 100644 arch/riscv/kernel/asm-offsets.c
create mode 100644 arch/riscv/kernel/cacheinfo.c
create mode 100644 arch/riscv/kernel/cpu.c
create mode 100644 arch/riscv/kernel/cpufeature.c
create mode 100644 arch/riscv/kernel/entry.S
create mode 100644 arch/riscv/kernel/head.S
create mode 100644 arch/riscv/kernel/irq.c
create mode 100644 arch/riscv/kernel/module.c
create mode 100644 arch/riscv/kernel/process.c
create mode 100644 arch/riscv/kernel/ptrace.c
create mode 100644 arch/riscv/kernel/reset.c
create mode 100644 arch/riscv/kernel/riscv_ksyms.c
create mode 100644 arch/riscv/kernel/setup.c
create mode 100644 arch/riscv/kernel/signal.c
create mode 100644 arch/riscv/kernel/smp.c
create mode 100644 arch/riscv/kernel/smpboot.c
create mode 100644 arch/riscv/kernel/stacktrace.c
create mode 100644 arch/riscv/kernel/sys_riscv.c
create mode 100644 arch/riscv/kernel/syscall_table.c
create mode 100644 arch/riscv/kernel/time.c
create mode 100644 arch/riscv/kernel/traps.c
create mode 100644 arch/riscv/kernel/vdso.c
create mode 100644 arch/riscv/kernel/vdso/.gitignore
create mode 100644 arch/riscv/kernel/vdso/Makefile
create mode 100644 arch/riscv/kernel/vdso/rt_sigreturn.S
create mode 100644 arch/riscv/kernel/vdso/vdso.S
create mode 100644 arch/riscv/kernel/vdso/vdso.lds.S
create mode 100644 arch/riscv/kernel/vmlinux.lds.S
create mode 100644 arch/riscv/lib/Makefile
create mode 100644 arch/riscv/lib/delay.c
create mode 100644 arch/riscv/lib/memcpy.S
create mode 100644 arch/riscv/lib/memset.S
create mode 100644 arch/riscv/lib/uaccess.S
create mode 100644 arch/riscv/lib/udivdi3.S
create mode 100644 arch/riscv/mm/Makefile
create mode 100644 arch/riscv/mm/extable.c
create mode 100644 arch/riscv/mm/fault.c
create mode 100644 arch/riscv/mm/init.c
create mode 100644 arch/riscv/mm/ioremap.c
create mode 100644 include/lib/libgcc.h
create mode 100644 lib/ashldi3.c
create mode 100644 lib/ashrdi3.c
create mode 100644 lib/cmpdi2.c
create mode 100644 lib/lshrdi3.c
create mode 100644 lib/muldi3.c
create mode 100644 lib/ucmpdi2.c
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