lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Tue, 14 Nov 2017 08:09:54 -0800 From: tip-bot for Kan Liang <tipbot@...or.com> To: linux-tip-commits@...r.kernel.org Cc: eranian@...gle.com, linux-kernel@...r.kernel.org, hpa@...or.com, kan.liang@...el.com, tglx@...utronix.de, mingo@...nel.org Subject: [tip:perf/urgent] perf/x86/intel/uncore: Add event constraint for BDX PCU Commit-ID: bb9fbe1b57503f790dbbf9f06e72cb0fb9e60740 Gitweb: https://git.kernel.org/tip/bb9fbe1b57503f790dbbf9f06e72cb0fb9e60740 Author: Kan Liang <kan.liang@...el.com> AuthorDate: Tue, 14 Nov 2017 06:06:40 -0800 Committer: Thomas Gleixner <tglx@...utronix.de> CommitDate: Tue, 14 Nov 2017 17:07:49 +0100 perf/x86/intel/uncore: Add event constraint for BDX PCU Event select bit 7 'Use Occupancy' in PCU Box is not available for counter 0 on BDX Add a constraint to fix it. Reported-by: Stephane Eranian <eranian@...gle.com> Signed-off-by: Kan Liang <kan.liang@...el.com> Signed-off-by: Thomas Gleixner <tglx@...utronix.de> Tested-by: Stephane Eranian <eranian@...gle.com> Cc: peterz@...radead.org Cc: ak@...ux.intel.com Link: https://lkml.kernel.org/r/1510668400-301000-1-git-send-email-kan.liang@intel.com --- arch/x86/events/intel/uncore_snbep.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/x86/events/intel/uncore_snbep.c b/arch/x86/events/intel/uncore_snbep.c index 95cb19f..f4e4168 100644 --- a/arch/x86/events/intel/uncore_snbep.c +++ b/arch/x86/events/intel/uncore_snbep.c @@ -3035,11 +3035,19 @@ static struct intel_uncore_type *bdx_msr_uncores[] = { NULL, }; +/* Bit 7 'Use Occupancy' is not available for counter 0 on BDX */ +static struct event_constraint bdx_uncore_pcu_constraints[] = { + EVENT_CONSTRAINT(0x80, 0xe, 0x80), + EVENT_CONSTRAINT_END +}; + void bdx_uncore_cpu_init(void) { if (bdx_uncore_cbox.num_boxes > boot_cpu_data.x86_max_cores) bdx_uncore_cbox.num_boxes = boot_cpu_data.x86_max_cores; uncore_msr_uncores = bdx_msr_uncores; + + hswep_uncore_pcu.constraints = bdx_uncore_pcu_constraints; } static struct intel_uncore_type bdx_uncore_ha = {
Powered by blists - more mailing lists