linux-kernel - Re: [RFC 6/7] x86/asm: Remap the TSS into the cpu entry area

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Message-ID: <CALCETrWozKE0nHWiyF_V4UU7hr_TWS2AFLbOJ15ZZqQYhCG8NA@mail.gmail.com>
Date:   Mon, 13 Nov 2017 18:30:07 -0800
From:   Andy Lutomirski <luto@...nel.org>
To:     Linus Torvalds <torvalds@...ux-foundation.org>
Cc:     Andy Lutomirski <luto@...nel.org>,
        Dave Hansen <dave.hansen@...el.com>, X86 ML <x86@...nel.org>,
        Borislav Petkov <bpetkov@...e.de>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Brian Gerst <brgerst@...il.com>
Subject: Re: [RFC 6/7] x86/asm: Remap the TSS into the cpu entry area

On Mon, Nov 13, 2017 at 6:28 PM, Linus Torvalds
<torvalds@...ux-foundation.org> wrote:
> On Mon, Nov 13, 2017 at 6:25 PM, Andy Lutomirski <luto@...nel.org> wrote:
>> On Mon, Nov 13, 2017 at 11:36 AM, Linus Torvalds
>> <torvalds@...ux-foundation.org> wrote:
>>>
>>> I forget what the actual size is, but aligning the hardware TSS struct
>>> to 128 bytes might be sufficient. It's not that big.
>>
>> 104 bytes, so it's probably already fine.  For anything except an
>> actual task switch, only the first 12 or so bytes matter.
>
> Note that historically, about half of the Intel errata (that don't get
> fixed) are about TSS in oddball situations, mainly page crossers.
>
> I may be exaggerating just a tiny bit, but it's definitely a "don't do it".

:)

I suspect the major case where this matters is when we do a task
switch, which only ever happens on 32-bit double faults, at which
point we're already seriously screwed.  But yes, I agree.