linux-kernel - Re: [PATCH] refcount: provide same memory ordering guarantees as in atomic

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20171115180540.GQ19071@arm.com>
Date:   Wed, 15 Nov 2017 18:05:41 +0000
From:   Will Deacon <will.deacon@....com>
To:     Alan Stern <stern@...land.harvard.edu>
Cc:     Peter Zijlstra <peterz@...radead.org>,
        "Reshetova, Elena" <elena.reshetova@...el.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "keescook@...omium.org" <keescook@...omium.org>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "ishkamiel@...il.com" <ishkamiel@...il.com>,
        Paul McKenney <paulmck@...ux.vnet.ibm.com>,
        parri.andrea@...il.com, boqun.feng@...il.com, dhowells@...hat.com,
        david@...morbit.com
Subject: Re: [PATCH] refcount: provide same memory ordering guarantees as in
 atomic_t

On Thu, Nov 02, 2017 at 04:21:56PM -0400, Alan Stern wrote:
> I was trying to think of something completely different.  If you have a
> release/acquire to the same address, it creates a happens-before
> ordering:
> 
> 	Access x
> 	Release a
> 	Acquire a
> 	Access y
> 
> Here is the access to x happens-before the access to y.  This is true
> even on x86, even in the presence of forwarding -- the CPU still has to
> execute the instructions in order.  But if the release and acquire are
> to different addresses:
> 
> 	Access x
> 	Release a
> 	Acquire b
> 	Access y
> 
> then there is no happens-before ordering for x and y -- the CPU can
> execute the last two instructions before the first two.  x86 and
> PowerPC won't do this, but I believe ARMv8 can.  (Please correct me if
> it can't.)

Release/Acquire are RCsc on ARMv8, so they are ordered irrespective of
address.

Will