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Message-ID: <20171116100222.k3zic3ut3ectnaly@pd.tnic>
Date:   Thu, 16 Nov 2017 11:02:22 +0100
From:   Borislav Petkov <bp@...en8.de>
To:     Steve Rutherford <srutherford@...gle.com>
Cc:     Brijesh Singh <brijesh.singh@....com>, x86@...nel.org,
        KVM list <kvm@...r.kernel.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...e.de>,
        Andy Lutomirski <luto@...nel.org>,
        Tom Lendacky <thomas.lendacky@....com>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim KrĠmář 
        <rkrcmar@...hat.com>
Subject: Re: [Part1 PATCH v7 00/17] x86: Secure Encrypted Virtualization (AMD)

On Wed, Nov 15, 2017 at 03:57:13PM -0800, Steve Rutherford wrote:
> One piece that seems missing here is the handling of the vmm
> communication exception. What's the plan for non-automatic exits? In
> particular, what's the plan for emulated devices that are currently
> accessed through MMIO (e.g. the IOAPIC)?

First of all, please do not top-post.

Then, maybe this would answer some of your questions:

http://support.amd.com/TechDocs/Protecting%20VM%20Register%20State%20with%20SEV-ES.pdf

But I'd look in Tom's direction for further comments.

> Maybe I'm getting ahead of myself: What's the testing story? (since I
> don't think linux would boot with these patches, I'm curious what you
> are doing to ensure these pieces work)

Seems to boot fine here :)

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

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