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Message-ID: <mhng-caa01618-0bb9-441c-9ed1-9baf49b86a20@palmer-si-x1c4>
Date:   Tue, 21 Nov 2017 09:41:14 -0800 (PST)
From:   Palmer Dabbelt <palmer@...ive.com>
To:     robh@...nel.org
CC:     mark.rutland@....com, devicetree@...r.kernel.org,
        patches@...ups.riscv.org, linux-kernel@...r.kernel.org
Subject:     Re: [patches] Re: [PATCH] dt-bindings: Add an enable method to RISC-V
On Mon, 20 Nov 2017 13:47:09 PST (-0800), robh@...nel.org wrote:
> On Mon, Nov 20, 2017 at 11:50:22AM -0800, Palmer Dabbelt wrote:
>> RISC-V doesn't currently specify a mechanism for enabling or disabling
>> CPUs.  Instead, we assume that all CPUs are enabled on boot, and if
>> someone wants to save power we instead put a CPU to sleep via a WFI
>> loop.
>>
>> This patch adds "enable-method" to the RISC-V CPU binding, which
>> currently only has the value "none".  This allows us to change the
>> enable method in the future.
>
> I think "none" should just be no cpu-enable-method property.
I'm OK with that.
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