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Message-ID: <5a14cf7a.WQSAjmhcynG7fOAx%fengguang.wu@intel.com>
Date: Wed, 22 Nov 2017 09:14:34 +0800
From: kernel test robot <fengguang.wu@...el.com>
To: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: LKP <lkp@...org>, linux-kernel@...r.kernel.org,
Ingo Molnar <mingo@...nel.org>, wfg@...ux.intel.com
Subject: ceb81cbc32 ("x86/mm/tlb: Make CR4-based TLB flushes more
robust"): WARNING: CPU: 0 PID: 0 at arch/x86/include/asm/tlbflush.h:258
native_flush_tlb_global
Greetings,
0day kernel testing robot got the below dmesg and the first bad commit is
https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git WIP.x86/mm
commit ceb81cbc32994ef460436fc4296c97bed5bfce46
Author: Dave Hansen <dave.hansen@...ux.intel.com>
AuthorDate: Fri Nov 10 11:31:01 2017 -0800
Commit: Ingo Molnar <mingo@...nel.org>
CommitDate: Tue Nov 21 09:35:22 2017 +0100
x86/mm/tlb: Make CR4-based TLB flushes more robust
The existing CR4-based TLB flush currently requires global pages
to be supported *and* enabled. But, the hardware only needs for
them to be supported.
Make the code more robust by allowing the initial state of
X86_CR4_PGE to be on *or* off. In addition, if called in an
unexpected state (X86_CR4_PGE=0), issue a warning. X86_CR4_PGE=0
is certainly unexpected should not be ignored it if encountered.
This essentially gives the best of both worlds: a TLB flush no
matter what, and a warning if the TLB flush is called in an
unexpected way (X86_CR4_PGE=0).
The XOR change was suggested by Kirill Shutemov.
Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>
Cc: Andy Lutomirski <luto@...nel.org>
Cc: Daniel Gruss <daniel.gruss@...k.tugraz.at>
Cc: Hugh Dickins <hughd@...gle.com>
Cc: Kees Cook <keescook@...gle.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Michael Schwarz <michael.schwarz@...k.tugraz.at>
Cc: Moritz Lipp <moritz.lipp@...k.tugraz.at>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Richard Fellner <richard.fellner@...dent.tugraz.at>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: linux-mm@...ck.org
Link: http://lkml.kernel.org/r/20171110193101.B4285C6A@viggo.jf.intel.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
b03044186b x86/mm: Do not set _PAGE_USER for init_mm page tables
ceb81cbc32 x86/mm/tlb: Make CR4-based TLB flushes more robust
d44595c882 x86/entry/64: Fix build warning in syscall_init()
b8b9930e8e Merge branch 'WIP.x86/mm'
+---------------------------------------------------------------------+------------+------------+------------+------------+
| | b03044186b | ceb81cbc32 | d44595c882 | b8b9930e8e |
+---------------------------------------------------------------------+------------+------------+------------+------------+
| boot_successes | 34 | 0 | 0 | 0 |
| boot_failures | 1 | 15 | 19 | 17 |
| WARNING:at_mm/vmalloc.c:#vmalloc_to_page | 1 | | | |
| EIP:vmalloc_to_page | 1 | | | |
| WARNING:at_arch/x86/include/asm/tlbflush.h:#native_flush_tlb_global | 0 | 15 | 19 | 17 |
| EIP:native_flush_tlb_global | 0 | 15 | 19 | 17 |
| WARNING:at_kernel/jump_label.c:#jump_label_test | 0 | 0 | 1 | |
| EIP:jump_label_test | 0 | 0 | 1 | |
+---------------------------------------------------------------------+------------+------------+------------+------------+
Decompressing Linux... Parsing ELF... Performing relocations... done.
Booting the kernel.
[ 0.000000] Linux version 4.14.0-01209-gceb81cb (kbuild@...-g5) (gcc version 5.4.1 20171010 (Debian 5.5.0-3)) #2 SMP Wed Nov 22 05:57:00 CST 2017
[ 0.000000] ------------[ cut here ]------------
[ 0.000000] WARNING: CPU: 0 PID: 0 at arch/x86/include/asm/tlbflush.h:258 native_flush_tlb_global+0x30/0x77
[ 0.000000] Modules linked in:
[ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 4.14.0-01209-gceb81cb #2
[ 0.000000] task: 4f3c1800 task.stack: 4f3b8000
[ 0.000000] EIP: native_flush_tlb_global+0x30/0x77
[ 0.000000] EFLAGS: 00210046 CPU: 0
[ 0.000000] EAX: 00000020 EBX: 5f60f203 ECX: 00200046 EDX: 4f3ba008
[ 0.000000] ESI: 4f63a7e4 EDI: 4f43ec24 EBP: 4f3b9f0c ESP: 4f3b9ef4
[ 0.000000] DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
[ 0.000000] CR0: 80050033 CR2: 00000000 CR3: 0f637000 CR4: 00000020
[ 0.000000] Call Trace:
[ 0.000000] ? setup_arch+0x120/0xdea
[ 0.000000] ? start_kernel+0x66/0x50b
[ 0.000000] ? load_idt+0x9/0xb
[ 0.000000] ? i386_start_kernel+0xc2/0xda
[ 0.000000] ? startup_32_smp+0x164/0x168
[ 0.000000] Code: ec 14 65 a1 14 00 00 00 89 45 f8 31 c0 e9 4e 61 67 00 eb 2e e8 97 fc ff ff 89 c1 ff 15 04 1b 3d 4f 64 a1 8c da 62 4f a8 80 75 02 <0f> ff 89 c2 80 f2 80 0f 22 e2 0f 22 e0 89 c8 ff 15 00 1b 3d 4f
[ 0.000000] random: get_random_bytes called from init_oops_id+0x23/0x3b with crng_init=0
[ 0.000000] ---[ end trace 0000000000000000 ]---
[ 0.000000] KERNEL supported cpus:
# HH:MM RESULT GOOD BAD GOOD_BUT_DIRTY DIRTY_NOT_BAD
git bisect start e953623845d0d1fa85d6b8ff50f8df5e1756a49f bebc6082da0a9f5d47a1ea2edc099bf671058bd4 --
git bisect good 0ea6c9d73a9b188a9fa1549ae47d418b9cb7327b # 01:57 G 11 0 0 0 Merge 'peterz-queue/sched/urgent' into devel-catchup-201711212335
git bisect bad 32955e880edf042e58f0a56407ecc9300c7ac531 # 02:08 B 0 11 25 0 Merge 'peterz-queue/WIP.timers' into devel-catchup-201711212335
git bisect good 7b99cde213c95999c60d9f1f9c8567f3e60a9e93 # 02:58 G 10 0 1 1 Merge 'peterz-queue/perf/core' into devel-catchup-201711212335
git bisect bad ff7d29ebc875174c9b54c403c2d9efc74fe74dcb # 03:14 B 0 2 16 0 Merge 'peterz-queue/master' into devel-catchup-201711212335
git bisect good 270583ab64c9f60f1f5056c1a9eb81c5b8b8f870 # 03:38 G 10 0 0 0 Merge branch 'x86/urgent'
git bisect bad e169c4425862cc27bc67eea597284365f6e6228b # 05:03 B 0 7 25 4 x86/entry/64: Use a percpu trampoline stack for IDT entries
git bisect bad 654008e0114942f6a0ba7acf61815146131210ad # 05:18 B 0 7 21 0 x86/fixmap: Generalize the GDT fixmap mechanism
git bisect bad 898cd198c42235c00276b6d7176a25769d367f49 # 05:43 B 0 1 19 4 x86/mm: Document X86_CR4_PGE toggling behavior
git bisect bad ceb81cbc32994ef460436fc4296c97bed5bfce46 # 06:32 B 0 3 21 4 x86/mm/tlb: Make CR4-based TLB flushes more robust
git bisect good b03044186b0a98a76daaa50aef336bb09f1fb8dc # 07:00 G 10 0 1 1 x86/mm: Do not set _PAGE_USER for init_mm page tables
# first bad commit: [ceb81cbc32994ef460436fc4296c97bed5bfce46] x86/mm/tlb: Make CR4-based TLB flushes more robust
git bisect good b03044186b0a98a76daaa50aef336bb09f1fb8dc # 07:50 G 30 0 0 1 x86/mm: Do not set _PAGE_USER for init_mm page tables
# extra tests with debug options
git bisect bad ceb81cbc32994ef460436fc4296c97bed5bfce46 # 08:03 B 0 1 15 1 x86/mm/tlb: Make CR4-based TLB flushes more robust
# extra tests on HEAD of linux-devel/devel-catchup-201711212335
git bisect bad e953623845d0d1fa85d6b8ff50f8df5e1756a49f # 08:09 B 0 13 30 0 0day head guard for 'devel-catchup-201711212335'
# extra tests on tree/branch tip/WIP.x86/mm
git bisect bad d44595c88270b4d6b829f5ebd5d8b4cb0402dc41 # 08:38 B 0 11 33 8 x86/entry/64: Fix build warning in syscall_init()
# extra tests on tree/branch tip/master
git bisect bad b8b9930e8ee55c65e167e0c4aca2ac140ed3c8d3 # 09:12 B 0 9 31 8 Merge branch 'WIP.x86/mm'
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/lkp Intel Corporation
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