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Message-ID: <mhng-55eb51de-8c76-4dd1-b699-5ce082ed0dd2@palmer-si-x1c4>
Date: Wed, 22 Nov 2017 09:38:16 -0800 (PST)
From: Palmer Dabbelt <palmer@...ive.com>
To: David.Laight@...LAB.COM
CC: linux-kernel@...r.kernel.org, patches@...ups.riscv.org,
Andrew Waterman <andrew@...ive.com>
Subject: Re: [patches] RE: [PATCH 3/4] RISC-V: Flush I$ when making a dirty page executable
On Tue, 21 Nov 2017 08:57:07 PST (-0800), David.Laight@...LAB.COM wrote:
> From: Palmer Dabbelt
>> Sent: 20 November 2017 18:58
>>
>> The RISC-V ISA allows for instruction caches that are not coherent WRT
>> stores, even on a single hart. As a result, we need to explicitly flush
>> the instruction cache whenever marking a dirty page as executable in
>> order to preserve the correct system behavior.
>
> Isn't the I-flush only needed if there has been an unmap since the
> previous I-flush?
> Since code is rarely unmapped (exec and driver unload come to mind)
> the I-flush won't be needed very often.
There's nothing in the RISC-V ISA that prevents the instruction cache from
caching read-only (or even unmapped!) pages. Instructions fetched this manner
could never commit, but they could fill up the icache with garbage. I believe
that means we need to flush on dirty->execute, but if I'm wrong I'm happy to
change it.
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