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Date:   Thu, 23 Nov 2017 19:13:21 +0100
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Adrian Hunter <adrian.hunter@...el.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-msm@...r.kernel.org" <linux-arm-msm@...r.kernel.org>,
        Stephen Boyd <sboyd@...eaurora.org>,
        Sahitya Tummala <stummala@...eaurora.org>,
        Vijay Viswanath <vviswana@...eaurora.org>
Subject: Re: [PATCH v2] mmc: sdhci-msm: Optionally wait for signal level changes

On 20 November 2017 at 20:56, Bjorn Andersson
<bjorn.andersson@...aro.org> wrote:
> Not all instances of the SDCC core supports changing signal voltage and
> as such will not generate a power interrupt when the software attempts
> to change the voltage. This results in probing the eMMC on some devices
> to take over 2 minutes.
>
> Check that the SWITCHABLE_SIGNALING_VOLTAGE bit in MCI_GENERICS is set
> before waiting for the power interrupt.
>
> Cc: Sahitya Tummala <stummala@...eaurora.org>
> Cc: Vijay Viswanath <vviswana@...eaurora.org>
> Fixes: c0309b3803fe ("mmc: sdhci-msm: Add sdhci msm register write APIs which wait for pwr irq")
> Signed-off-by: Bjorn Andersson <bjorn.andersson@...aro.org>

Thanks, applied for fixes!

Kind regards
Uffe

> ---
>
> The offending patch is part of your v4.15 pull request, so please pick
> this up for the -rcs.
>
> Changes since v1:
> - Fixed spelling of swichable...
>
>  drivers/mmc/host/sdhci-msm.c | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
> index 3fb7d2eec93f..c283291db705 100644
> --- a/drivers/mmc/host/sdhci-msm.c
> +++ b/drivers/mmc/host/sdhci-msm.c
> @@ -29,6 +29,9 @@
>  #define CORE_VERSION_MAJOR_MASK                (0xf << CORE_VERSION_MAJOR_SHIFT)
>  #define CORE_VERSION_MINOR_MASK                0xff
>
> +#define CORE_MCI_GENERICS              0x70
> +#define SWITCHABLE_SIGNALING_VOLTAGE   BIT(29)
> +
>  #define CORE_HC_MODE           0x78
>  #define HC_MODE_EN             0x1
>  #define CORE_POWER             0x0
> @@ -1028,11 +1031,22 @@ static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type)
>         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>         struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
>         bool done = false;
> +       u32 val;
>
>         pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
>                         mmc_hostname(host->mmc), __func__, req_type,
>                         msm_host->curr_pwr_state, msm_host->curr_io_level);
>
> +       /*
> +        * The power interrupt will not be generated for signal voltage
> +        * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
> +        */
> +       val = readl(msm_host->core_mem + CORE_MCI_GENERICS);
> +       if ((req_type & REQ_IO_HIGH || req_type & REQ_IO_LOW) &&
> +           !(val & SWITCHABLE_SIGNALING_VOLTAGE)) {
> +               return;
> +       }
> +
>         /*
>          * The IRQ for request type IO High/LOW will be generated when -
>          * there is a state change in 1.8V enable bit (bit 3) of
> --
> 2.15.0
>

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