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Date:   Mon, 27 Nov 2017 10:28:04 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Wu Hao' <hao.wu@...el.com>, "atull@...nel.org" <atull@...nel.org>,
        "mdf@...nel.org" <mdf@...nel.org>,
        "linux-fpga@...r.kernel.org" <linux-fpga@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
CC:     "linux-api@...r.kernel.org" <linux-api@...r.kernel.org>,
        "luwei.kang@...el.com" <luwei.kang@...el.com>,
        "yi.z.zhang@...el.com" <yi.z.zhang@...el.com>,
        Tim Whisonant <tim.whisonant@...el.com>,
        "Enno Luebbers" <enno.luebbers@...el.com>,
        Shiva Rao <shiva.rao@...el.com>,
        Christopher Rauer <christopher.rauer@...el.com>,
        Xiao Guangrong <guangrong.xiao@...ux.intel.com>
Subject: RE: [PATCH v3 08/21] fpga: add Intel FPGA DFL PCIe device

From: Wu Hao
> Sent: 27 November 2017 06:42
> From: Zhang Yi <yi.z.zhang@...el.com>
> 
> The Intel FPGA device appears as a PCIe device on the system. This patch
> implements the basic framework of the driver for Intel PCIe device which
> is located between CPU and Accelerated Function Units (AFUs), and has
> the Device Feature List (DFL) implemented in its MMIO space.

This ought to have a better name than 'Intel FPGA'.
An fpga can be used for all sorts of things, this looks like
a very specific architecture using a common VHDL environment to
allow certain types of user VHDL be accessed over PCIe.

	David

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