linux-kernel - Re: [PATCH 15/24] x86/mm: Allow flushing for future ASID switches

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Message-ID: <20171128203949.iceajmil2cwvktho@hirez.programming.kicks-ass.net>
Date:   Tue, 28 Nov 2017 21:39:49 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Andy Lutomirski <luto@...capital.net>
Cc:     Dave Hansen <dave.hansen@...ux.intel.com>,
        Ingo Molnar <mingo@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H . Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...en8.de>,
        Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [PATCH 15/24] x86/mm: Allow flushing for future ASID switches

On Tue, Nov 28, 2017 at 12:34:17PM -0800, Andy Lutomirski wrote:
> Side question: on extremely quick read, you're doing bt then btr.  Why
> not just do a single btr and be done with it?  Are you trying to avoid
> getting exclusive access to the cacheline when not needed?

Yes, avoids the M in the common !flush case.