lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 30 Nov 2017 07:46:56 -0700
From:   "Jan Beulich" <JBeulich@...e.com>
To:     "Govinda Tatti" <govinda.tatti@...cle.com>
Cc:     <roger.pau@...rix.com>, <xen-devel@...ts.xenproject.org>,
        <boris.ostrovsky@...cle.com>, "Juergen Gross" <jgross@...e.com>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [Xen-devel] [PATCH V2] Xen/pciback: Implement PCI slot or
 bus reset with 'do_flr' SysFS attribute

>>> On 30.11.17 at 15:15, <govinda.tatti@...cle.com> wrote:
> On 11/30/2017 2:27 AM, Jan Beulich wrote:
>>>>> On 29.11.17 at 18:38, <govinda.tatti@...cle.com> wrote:
>>>>> In the case of bus or slot reset, our goal is to reset connected PCIe
>>>>> fabric/card/endpoint.
>>>>> The connected card/endpoint can be multi-function device. So, same
>>>>> walk-through and checking
>>>>> is needed irrespective of type of reset being used.
>>>> I don't follow: The scope of other devices/functions possibly
>>>> affected by a reset depends on the type of reset, doesn't it?
>>> For PCIe platforms, both slot and bus reset endup resetting all connected
>>> device/functions on thesecondary bus (behind the root-port or
>>> downstream-port).
>> According to my understanding this contradicts the comment
>> ahead of pci_reset_slot(), which talks of multiple slots per bus.
>> In such a setup, I can't see why resetting on slot would affect
>> other slots on the same bus. At the same time the comment
>> says that the slot reset may resolve to a bus one when there's
>> just a single slot on the bus.
> For legacy PCI/PCI-X, we can have multiple slots per bus but not with 
> PCI-Express
> (each link will be on a separate bus).

Is that true even for root complex integrated end points? A
random system's lspci output doesn't seem to agree with what
you say. A typical example would be USB controllers all sitting
on bus 0, but having different slot numbers. You clearly won't
be able to ever bus-reset these, and if you checked all devices
on bus 0 you would then also not be able to slot-reset them.

Jan

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ