linux-kernel - Re: [PATCH 15/24] x86/mm: Allow flushing for future ASID switches

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Message-ID: <20171130154414.aekkjd26p3hxyqwa@hirez.programming.kicks-ass.net>
Date:   Thu, 30 Nov 2017 16:44:14 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Ingo Molnar <mingo@...nel.org>
Cc:     linux-kernel@...r.kernel.org,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Andy Lutomirski <luto@...capital.net>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H . Peter Anvin" <hpa@...or.com>, Borislav Petkov <bp@...en8.de>,
        Linus Torvalds <torvalds@...ux-foundation.org>
Subject: Re: [PATCH 15/24] x86/mm: Allow flushing for future ASID switches

On Mon, Nov 27, 2017 at 11:49:14AM +0100, Ingo Molnar wrote:
> @@ -338,24 +366,23 @@ static inline void __native_flush_tlb_single(unsigned long addr)
>  
>  static inline void __flush_tlb_all(void)
>  {
> +	if (boot_cpu_has(X86_FEATURE_PGE)) {
>  		__flush_tlb_global();
> +	} else {
>  		__flush_tlb();
> +		tlb_flush_shared_nonglobals();

I do however think this one is superfluous; if we do not have PGE we
also do not have PCID and every CR3 switch flushes everything.

> +	}
>  }