lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 30 Nov 2017 19:54:08 -0600
From:   Rob Herring <robh@...nel.org>
To:     Alexandre Belloni <alexandre.belloni@...e-electrons.com>
Cc:     Ralf Baechle <ralf@...ux-mips.org>, linux-mips@...ux-mips.org,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-pm@...r.kernel.org
Subject: Re: [PATCH 06/13] dt-bindings: power: reset: Document ocelot-reset
 binding

On Tue, Nov 28, 2017 at 04:26:36PM +0100, Alexandre Belloni wrote:
> Add binding documentation for the Microsemi Ocelot reset block.
> 
> Signed-off-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
> ---
> Cc: Rob Herring <robh+dt@...nel.org>
> Cc: devicetree@...r.kernel.org
> To: Sebastian Reichel <sre@...nel.org>
> Cc: linux-pm@...r.kernel.org
> 
>  .../bindings/power/reset/ocelot-reset.txt          | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> 
> diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> new file mode 100644
> index 000000000000..2d3f2c21fadd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
> @@ -0,0 +1,24 @@
> +Microsemi Ocelot reset driver

Bindings are not drivers.

> +
> +The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
> +SoC MIPS core.
> +
> +Required Properties:
> + - compatible: "mscc,ocelot-chip-reset"
> + - mscc,cpucontrol: phandle to the CPU system control syscon block
> +
> +Example:
> +		cpu_ctrl: syscon@...00000 {
> +			compatible = "syscon";

syscon alone is not valid.

> +			reg = <0x70000000 0x2c>;
> +		};
> +
> +		syscon@...70000 {
> +			compatible = "simple-mfd", "syscon";

SoC specific compatible?

> +			reg = <0x71070000 0x1c>;
> +
> +			reset {
> +				compatible = "mscc,ocelot-chip-reset";
> +				mscc,cpucontrol = <&cpu_ctrl>;

This looks strange. A syscon pointing to another syscon?

Doesn't look like you even need this node, but hard to know if you don't 
document the parent node completely (i.e. what are all the functions in 
this syscon).

> +			};
> +		};
> -- 
> 2.15.0
> 

Powered by blists - more mailing lists