linux-kernel - [tip:ras/core] x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF

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Date:   Mon, 4 Dec 2017 11:44:14 -0800
From:   tip-bot for Yazen Ghannam <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     bp@...e.de, tony.luck@...el.com, tglx@...utronix.de,
        yazen.ghannam@....com, hpa@...or.com, mingo@...nel.org,
        linux-kernel@...r.kernel.org, linux-edac@...r.kernel.org
Subject: [tip:ras/core] x86/mce/AMD: Don't set DEF_INT_TYPE in
 MSR_CU_DEF_ERR on SMCA systems

Commit-ID:  c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Gitweb:     https://git.kernel.org/tip/c8a4364c33ac7ed63278267b8f6d8c15810d5fd1
Author:     Yazen Ghannam <yazen.ghannam@....com>
AuthorDate: Mon, 4 Dec 2017 17:54:38 +0100
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 4 Dec 2017 20:38:44 +0100

x86/mce/AMD: Don't set DEF_INT_TYPE in MSR_CU_DEF_ERR on SMCA systems

The McaIntrCfg register (MSRC000_0410), previously known as CU_DEFER_ERR,
is used on SMCA systems to set the LVT offset for the Threshold and
Deferred error interrupts.

This register was used on non-SMCA systems to also set the Deferred
interrupt type in bits 2:1. However, these bits are reserved on SMCA
systems.

Only set MSRC000_0410[2:1] on non-SMCA systems.

Signed-off-by: Yazen Ghannam <yazen.ghannam@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: Tony Luck <tony.luck@...el.com>
Cc: linux-edac <linux-edac@...r.kernel.org>
Link: http://lkml.kernel.org/r/20171120162646.5210-1-Yazen.Ghannam@amd.com

---
 arch/x86/kernel/cpu/mcheck/mce_amd.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_amd.c b/arch/x86/kernel/cpu/mcheck/mce_amd.c
index 486f640..a38ab1f 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_amd.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_amd.c
@@ -407,7 +407,9 @@ static void deferred_error_interrupt_enable(struct cpuinfo_x86 *c)
 	    (deferred_error_int_vector != amd_deferred_error_interrupt))
 		deferred_error_int_vector = amd_deferred_error_interrupt;
 
-	low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+	if (!mce_flags.smca)
+		low = (low & ~MASK_DEF_INT_TYPE) | DEF_INT_TYPE_APIC;
+
 	wrmsr(MSR_CU_DEF_ERR, low, high);
 }