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Message-ID: <3c0dca03-bf9e-8747-8c31-546172f88d6f@codeaurora.org>
Date: Tue, 5 Dec 2017 15:53:04 +0530
From: Vivek Gautam <vivek.gautam@...eaurora.org>
To: Manu Gautam <mgautam@...eaurora.org>,
Kishon Vijay Abraham I <kishon@...com>
Cc: linux-arm-msm@...r.kernel.org, linux-usb@...r.kernel.org,
Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
Stephen Boyd <sboyd@...eaurora.org>,
"open list:GENERIC PHY FRAMEWORK" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 07/16] phy: qcom-qusb2: Add support for different
register layouts
On 11/21/2017 02:53 PM, Manu Gautam wrote:
> New version of QUSB2 PHY has some registers offset changed.
> Add support to have register layout for a target and update
> the same in phy_configuration.
>
> Signed-off-by: Manu Gautam <mgautam@...eaurora.org>
> ---
> drivers/phy/qualcomm/phy-qcom-qusb2.c | 131 ++++++++++++++++++++++++----------
> 1 file changed, 95 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qusb2.c b/drivers/phy/qualcomm/phy-qcom-qusb2.c
> index 4a5b2a1..c0c5358 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qusb2.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qusb2.c
[snip]
> /*
> @@ -198,7 +249,8 @@ static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
We need to add following change to qusb2_phy_set_tune2_param()
since we have register layout now.
@@ -333,7 +334,7 @@ static void qusb2_phy_set_tune2_param(struct
qusb2_phy *qphy)
}
/* Fused TUNE2 value is the higher nibble only */
- qusb2_setbits(qphy->base, QUSB2PHY_PORT_TUNE2, val[0] << 0x4);
+ qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], val[0]
<< 0x4);
}
regards
Vivek
--
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