lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 5 Dec 2017 19:33:14 +0200
From:   Ville Syrjälä <ville.syrjala@...ux.intel.com>
To:     Sean Paul <seanpaul@...omium.org>
Cc:     dri-devel@...ts.freedesktop.org, intel-gfx@...ts.freedesktop.org,
        seanpaul@...gle.com, David Airlie <airlied@...ux.ie>,
        linux-kernel@...r.kernel.org,
        Rodrigo Vivi <rodrigo.vivi@...el.com>, daniel.vetter@...el.com
Subject: Re: [Intel-gfx] [PATCH v3 6/9] drm/i915: Make use of indexed write
 GMBUS feature

On Tue, Dec 05, 2017 at 12:15:05AM -0500, Sean Paul wrote:
> This patch enables the indexed write feature of the GMBUS to concatenate
> 2 consecutive messages into one. The criteria for an indexed write is
> that both messages are writes, the first is length == 1, and the second
> is length > 0. The first message is sent out by the GMBUS as the slave
> command, and the second one is sent via the GMBUS FIFO as usual.
> 
> Changes in v3:
> - Added to series
> 
> Suggested-by: Ville Syrjälä <ville.syrjala@...ux.intel.com>
> Signed-off-by: Sean Paul <seanpaul@...omium.org>
> ---
>  drivers/gpu/drm/i915/intel_i2c.c | 39 ++++++++++++++++++++++++++++++++++-----
>  1 file changed, 34 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index 49fdf09f9919..7399009aee0a 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -373,7 +373,8 @@ gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
>  
>  static int
>  gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
> -		       unsigned short addr, u8 *buf, unsigned int len)
> +		       unsigned short addr, u8 *buf, unsigned int len,
> +		       u32 gmbus1_index)
>  {
>  	unsigned int chunk_size = len;
>  	u32 val, loop;
> @@ -386,7 +387,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>  
>  	I915_WRITE_FW(GMBUS3, val);
>  	I915_WRITE_FW(GMBUS1,
> -		      GMBUS_CYCLE_WAIT |
> +		      gmbus1_index | GMBUS_CYCLE_WAIT |
>  		      (chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
>  		      (addr << GMBUS_SLAVE_ADDR_SHIFT) |
>  		      GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
> @@ -409,7 +410,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
>  }
>  
>  static int
> -gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
> +gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
> +		 u32 gmbus1_index)
>  {
>  	u8 *buf = msg->buf;
>  	unsigned int tx_size = msg->len;
> @@ -419,7 +421,8 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
>  	do {
>  		len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
>  
> -		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
> +		ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len,
> +					     gmbus1_index);
>  		if (ret)
>  			return ret;
>  
> @@ -430,6 +433,14 @@ gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
>  	return 0;
>  }
>  
> +static int
> +gmbus_xfer_index_write(struct drm_i915_private *dev_priv, u8 cmd,
> +		       struct i2c_msg *msg)
> +{
> +	u8 gmbus1_index = GMBUS_CYCLE_INDEX | (cmd << GMBUS_SLAVE_INDEX_SHIFT);
> +	return gmbus_xfer_write(dev_priv, msg, gmbus1_index);
> +}

Instead of a duplicating the entire thing I'd just

- gmbus_xfer_index_read
+ gmbus_xfer_index
  {
  ...
+ 	if (msgs[1].flags & I2C_M_RD)
		gmbus_xfer_read()
+ 	else
+ 		gmbus_xfer_write()
  ...
  }

Matches the current pattern better (no 'cmd' passed in), and
will give us the 2 byte index for free as well.

> +
>  /*
>   * The gmbus controller can combine a 1 or 2 byte write with a read that
>   * immediately follows it by using an "INDEX" cycle.
> @@ -444,6 +455,20 @@ gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
>  		(msgs[i + 1].flags & I2C_M_RD));
>  }
>  
> +/*
> + * The gmbus controller can combine a 2-msg write into a single write that
> + * immediately follows it by using an "INDEX" cycle.
> + */
> +static bool
> +gmbus_is_index_write(struct i2c_msg *msgs, int i, int num)
> +{
> +	return (i + 1 < num &&
> +		msgs[i].addr == msgs[i + 1].addr &&
> +		!(msgs[i].flags & I2C_M_RD) &&
> +		!(msgs[i + 1].flags & I2C_M_RD) &&
> +		(msgs[i].len == 1 || msgs[i + 1].len > 0));

Hmm. We don't have the len check for the second msg for reads. I wonder
if gmbus can actually do a zero length "read/write"?

> +}
> +
>  static int
>  gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
>  {
> @@ -489,10 +514,14 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
>  		if (gmbus_is_index_read(msgs, i, num)) {
>  			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
>  			inc = 2; /* an index read is two msgs */
> +		} else if (gmbus_is_index_write(msgs, i, num)) {
> +			ret = gmbus_xfer_index_write(dev_priv, msgs[i].buf[0],
> +					&msgs[i + 1]);
> +			inc = 2; /* an index write is two msgs */
>  		} else if (msgs[i].flags & I2C_M_RD) {
>  			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
>  		} else {
> -			ret = gmbus_xfer_write(dev_priv, &msgs[i]);
> +			ret = gmbus_xfer_write(dev_priv, &msgs[i], 0);
>  		}
>  
>  		if (!ret)
> -- 
> 2.15.0.531.g2ccb3012c9-goog
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@...ts.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel OTC

Powered by blists - more mailing lists