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Date:   Wed, 6 Dec 2017 09:38:05 +0000
From:   Dhaval Rajeshbhai Shah <>
To:     'Greg KH' <>
CC:     "" <>,
        "" <>,
        "" <>,
        Hyun Kwon <>
Subject: RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
 logicoreIP init driver

> -----Original Message-----
> From: 'Greg KH' []
> Sent: Wednesday, December 06, 2017 1:16 AM
> To: Dhaval Rajeshbhai Shah <>
> Cc:;;;
> Hyun Kwon <>
> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU
> logicoreIP init driver
> On Wed, Dec 06, 2017 at 09:05:51AM +0000, Dhaval Rajeshbhai Shah wrote:
> > > Then you need to explain this a lot better, posting a random driver
> > > for submission that is expected to be used by another one isn't ok.
> > > Post the whole patch series please, we do not add infrastructure to
> > > the kernel that is not used right then.
> > Can I remove the export api and header file and make this driver generic
> for the logicoreIP? No other driver will depend on that. This will help us to
> remove the isolation between the Programmable system and Programmable
> logic by configuring the logicoreIp register set.
> I don't know, let's see what that patch submission looks like.  If it doesn't do
> anything, that's not really a good idea :)
This will do the isolation enable and removal related stuff along with the set the proper frequency based on the clock information get from the logicoreIp. In this way, This is very helpful driver.
> What's wrong with just submitting your entire driver series?  Why break it up
> like this?  That's normally not a good idea, you want us to review it in a
> "whole" idea, not piece-meal.
Codecs are owned by different team. when they will submit their code they will extend this driver.

> thanks,
> greg k-h

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