linux-kernel - Re: [PATCH RFC 1/2] perf/x86/intel: make reusable LBR initialization code

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 6 Dec 2017 13:51:14 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     Jan Dakinevich <jan.dakinevich@...tuozzo.com>
Cc:     linux-kernel@...r.kernel.org,
        "Denis V . Lunev" <den@...tuozzo.com>,
        Roman Kagan <rkagan@...tuozzo.com>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Kan Liang <kan.liang@...el.com>,
        Stephane Eranian <eranian@...gle.com>,
        Zhou Chengming <zhouchengming1@...wei.com>,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Colin King <colin.king@...onical.com>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jin Yao <yao.jin@...ux.intel.com>, kvm@...r.kernel.org
Subject: Re: [PATCH RFC 1/2] perf/x86/intel: make reusable LBR initialization
 code

On Wed, Dec 06, 2017 at 02:43:02PM +0300, Jan Dakinevich wrote:
> This patch introduces globally visible intel_pmu_lbr_fill() routine,
> which gathers information which LBR MSRs are support for specific CPU
> family/model.
> 
> It is supposed that the routine would be used in KVM code, using guest
> CPU information as an input. By this reason, it should not have any side
> effect which could affect host system.
> 
>  * LBR information moved to separate structure `struct x86_pmu_lbr';
>  * All family-specific tweaks on gathered information are applied only
>    for global x86_pmu.lbr to keep current perf initialization behavior.
> 
> Signed-off-by: Jan Dakinevich <jan.dakinevich@...tuozzo.com>

Hurch, that's a lot of churn. Nothing bad stood out though.