lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 6 Dec 2017 20:02:07 +0300
From:   Jan Dakinevich <jan.dakinevich@...tuozzo.com>
To:     Andi Kleen <ak@...ux.intel.com>
Cc:     <linux-kernel@...r.kernel.org>,
        "Denis V . Lunev" <den@...tuozzo.com>,
        Roman Kagan <rkagan@...tuozzo.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>, <x86@...nel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Kan Liang <kan.liang@...el.com>,
        Stephane Eranian <eranian@...gle.com>,
        Colin King <colin.king@...onical.com>,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Jin Yao <yao.jin@...ux.intel.com>, <kvm@...r.kernel.org>
Subject: Re: [PATCH RFC 2/2] KVM: x86/vPMU: ignore access to LBR-related
 MSRs

On Wed, 6 Dec 2017 07:57:28 -0800
Andi Kleen <ak@...ux.intel.com> wrote:

> 
> If you do all this it's only a small step to fully enable LBRs for
> guests. 

It is quite simple in a case where guest LBR-related MSRs matches host
ones. They could be handled by MSR load/store areas, I suppose.

In other cases, it could be expected the different amount of these MSRs
and different theirs base values (e.g. Nehalem vs Core). Guest MSRs
could be both subset and superset of host MSRs, so additional efforts
to support this would be required.

> 
> Just need to allow them to be written, expose PERF_CAPABILITIES too,
> and start/stop them on entry/exit, and enable context switching
> through perf in the host.
> 
> That would be far better than creating a frankenstate where LBR is
> there but mostly broken on some KVM versions.
> 
> -Andi



-- 
Best regards
Jan Dakinevich

Powered by blists - more mailing lists