lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Wed, 6 Dec 2017 09:29:20 -0800
From:   Brian Norris <briannorris@...omium.org>
To:     Enric Balletbo i Serra <enric.balletbo@...labora.com>
Cc:     MyungJoo Ham <myungjoo.ham@...sung.com>,
        Chanwoo Choi <cw00.choi@...sung.com>,
        Lee Jones <lee.jones@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Heiko Stuebner <heiko@...ech.de>, dianders@...gle.com,
        groeck@...omium.org, devicetree@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org,
        linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
        Alexandru Stan <amstan@...omium.org>,
        Jeffy Chen <jeffy.chen@...k-chips.com>,
        Frank Wang <frank.wang@...k-chips.com>
Subject: Re: [PATCH 3/3] arm64: dts: rockchip: add extcon nodes and enable
 tcphy.

+ Alex, Jeffy, Frank Wang

Hi,

On Wed, Dec 06, 2017 at 12:10:08PM +0100, Enric Balletbo i Serra wrote:
> Enable tcphy and create the cros-ec's extcon node for the USB Type-C port.
> 
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@...labora.com>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++
>  1 file changed, 26 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> index 470105d..03f1950 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
> @@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 {
>  			compatible = "google,cros-ec-pwm";
>  			#pwm-cells = <1>;
>  		};
> +
> +		usbc_extcon0: extcon@0 {
> +			compatible = "google,extcon-usbc-cros-ec";
> +			google,usb-port-id = <0>;
> +
> +			#extcon-cells = <0>;
> +		};
> +
> +		usbc_extcon1: extcon@1 {
> +			compatible = "google,extcon-usbc-cros-ec";
> +			google,usb-port-id = <1>;
> +
> +			#extcon-cells = <0>;
> +		};
>  	};
>  };
>  
> @@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 {
>  	rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
>  };
>  
> +&tcphy0 {
> +	status = "okay";
> +	extcon = <&usbc_extcon0>;
> +};
> +
> +&tcphy1 {
> +	status = "okay";
> +	extcon = <&usbc_extcon1>;
> +};
> +
>  &u2phy0 {
>  	status = "okay";
>  };
> @@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 {
>  
>  &usbdrd3_0 {
>  	status = "okay";
> +	extcon = <&usbc_extcon0>;
>  };
>  
>  &usbdrd_dwc3_0 {
> @@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 {
>  
>  &usbdrd3_1 {
>  	status = "okay";
> +	extcon = <&usbc_extcon1>;
>  };
>  
>  &usbdrd_dwc3_1 {

Seems OK.

Also, IIUC, I think if we ever want to support dual-role/OTG, we need an
extcon reference in the USB2/OTG PHY that serves these ports too. i.e.,
u2phy0 and u2phy1? Notably, the PHY driver supports the extcon
properties, but it's not documented in
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt yet (we
should probably get that fixed).

So, anyway, maybe the above isn't a blocker for this patch. Just noticed
it while reading. Assuming the driver stuff falls into place:

Reviewed-by: Brian Norris <briannorris@...omium.org>

Powered by blists - more mailing lists