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Message-ID: <CAOFm3uH4ibn972gdmESSvK1JS9H1MwHk-PWDvHkZc8yUUUN_eA@mail.gmail.com>
Date: Thu, 7 Dec 2017 22:47:05 +0100
From: Philippe Ombredanne <pombredanne@...b.com>
To: Dhaval Shah <dhaval.shah@...inx.com>
Cc: Arnd Bergmann <arnd@...db.de>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, LKML <linux-kernel@...r.kernel.org>,
michal.simek@...inx.com, hyunk@...inx.com,
Dhaval Shah <dshah@...inx.com>
Subject: Re: [PATCH v2 2/2] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver
Dear Dhaval,
On Thu, Dec 7, 2017 at 10:31 PM, Dhaval Shah <dhaval.shah@...inx.com> wrote:
> Xilinx ZYNQMP logicoreIP Init driver is based on the new
> LogiCoreIP design created. This driver provides the processing system
> and programmable logic isolation. Set the frequency based on the clock
> information get from the logicoreIP register set.
>
> It is put in drivers/misc as there is no subsystem for this logicoreIP.
>
> Signed-off-by: Dhaval Shah <dshah@...inx.com>
> ---
> Changes since v2:
> * Removed the "default n" from the Kconfig
> * More help text added to explain more about the logicoreIP driver
> * SPDX id is relocated at top of the file with // style comment
> * Removed the export API and header file and make it a single driver
> which provides logocoreIP init.
> * Provide the information in commit message as well for the why driver
> in drivers/misc.
Thank you for the SPDX comments updates.
Acked-by: Philippe Ombredanne <pombredanne@...b.com>
--
Cordially
Philippe Ombredanne
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