linux-kernel - [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding

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Message-Id: <20171208154618.20105-8-alexandre.belloni@free-electrons.com>
Date:   Fri,  8 Dec 2017 16:46:12 +0100
From:   Alexandre Belloni <alexandre.belloni@...e-electrons.com>
To:     Ralf Baechle <ralf@...ux-mips.org>
Cc:     linux-mips@...ux-mips.org, linux-kernel@...r.kernel.org,
        Alexandre Belloni <alexandre.belloni@...e-electrons.com>,
        Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
        Sebastian Reichel <sre@...nel.org>, linux-pm@...r.kernel.org
Subject: [PATCH v2 07/13] dt-bindings: power: reset: Document ocelot-reset binding

Add binding documentation for the Microsemi Ocelot reset block.

Cc: Rob Herring <robh+dt@...nel.org>
Cc: devicetree@...r.kernel.org
Cc: Sebastian Reichel <sre@...nel.org>
Cc: linux-pm@...r.kernel.org
Signed-off-by: Alexandre Belloni <alexandre.belloni@...e-electrons.com>
---
 .../devicetree/bindings/power/reset/ocelot-reset.txt    | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
new file mode 100644
index 000000000000..1bcf276b04cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt
@@ -0,0 +1,17 @@
+Microsemi Ocelot reset controller
+
+The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
+SoC MIPS core.
+
+Required Properties:
+ - compatible: "mscc,ocelot-chip-reset"
+
+Example:
+	syscon@...70000 {
+		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
+		reg = <0x71070000 0x1c>;
+
+		reset {
+			compatible = "mscc,ocelot-chip-reset";
+		};
+	};
-- 
2.15.1