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Message-Id: <20171208000934.6554-3-david.daney@cavium.com>
Date: Thu, 7 Dec 2017 16:09:29 -0800
From: David Daney <david.daney@...ium.com>
To: linux-mips@...ux-mips.org, ralf@...ux-mips.org,
James Hogan <james.hogan@...s.com>, netdev@...r.kernel.org,
"David S. Miller" <davem@...emloft.net>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>
Cc: linux-kernel@...r.kernel.org,
"Steven J. Hill" <steven.hill@...ium.com>,
devicetree@...r.kernel.org, Andrew Lunn <andrew@...n.ch>,
Florian Fainelli <f.fainelli@...il.com>,
Philippe Ombredanne <pombredanne@...b.com>,
Carlos Munoz <cmunoz@...ium.com>,
"Steven J . Hill" <Steven.Hill@...ium.com>,
David Daney <david.daney@...ium.com>
Subject: [PATCH v6 net-next,mips 2/7] MIPS: Octeon: Enable LMTDMA/LMTST operations.
From: Carlos Munoz <cmunoz@...ium.com>
LMTDMA/LMTST operations move data between cores and I/O devices:
* LMTST operations can send an address and a variable length
(up to 128 bytes) of data to an I/O device.
* LMTDMA operations can send an address and a variable length
(up to 128) of data to the I/O device and then return a
variable length (up to 128 bytes) response from the I/O device.
For both LMTST and LMTDMA, the data sent to the device is first stored
in the CVMSEG core local memory cache line indexed by
CVMMEMCTL[LMTLINE], the data is then atomically transmitted to the
device with a store to the CVMSEG LMTDMA trigger location.
Reviewed-by: James Hogan <jhogan@...nel.org>
Signed-off-by: Carlos Munoz <cmunoz@...ium.com>
Signed-off-by: Steven J. Hill <Steven.Hill@...ium.com>
Signed-off-by: David Daney <david.daney@...ium.com>
---
arch/mips/cavium-octeon/setup.c | 6 ++++++
arch/mips/include/asm/octeon/octeon.h | 12 ++++++++++--
2 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index a8034d0dcade..99e6a68bc652 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -609,6 +609,12 @@ void octeon_user_io_init(void)
#else
cvmmemctl.s.cvmsegenak = 0;
#endif
+ if (OCTEON_IS_OCTEON3()) {
+ /* Enable LMTDMA */
+ cvmmemctl.s.lmtena = 1;
+ /* Scratch line to use for LMT operation */
+ cvmmemctl.s.lmtline = 2;
+ }
/* R/W If set, CVMSEG is available for loads/stores in
* supervisor mode. */
cvmmemctl.s.cvmsegenas = 0;
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
index c99c4b6a79f4..92a17d67c1fa 100644
--- a/arch/mips/include/asm/octeon/octeon.h
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -179,7 +179,15 @@ union octeon_cvmemctl {
/* RO 1 = BIST fail, 0 = BIST pass */
__BITFIELD_FIELD(uint64_t wbfbist:1,
/* Reserved */
- __BITFIELD_FIELD(uint64_t reserved:17,
+ __BITFIELD_FIELD(uint64_t reserved_52_57:6,
+ /* When set, LMTDMA/LMTST operations are permitted */
+ __BITFIELD_FIELD(uint64_t lmtena:1,
+ /* Selects the CVMSEG LM cacheline used by LMTDMA
+ * LMTST and wide atomic store operations.
+ */
+ __BITFIELD_FIELD(uint64_t lmtline:6,
+ /* Reserved */
+ __BITFIELD_FIELD(uint64_t reserved_41_44:4,
/* OCTEON II - TLB replacement policy: 0 = bitmask LRU; 1 = NLU.
* This field selects between the TLB replacement policies:
* bitmask LRU or NLU. Bitmask LRU maintains a mask of
@@ -275,7 +283,7 @@ union octeon_cvmemctl {
/* R/W Size of local memory in cache blocks, 54 (6912
* bytes) is max legal value. */
__BITFIELD_FIELD(uint64_t lmemsz:6,
- ;)))))))))))))))))))))))))))))))))
+ ;))))))))))))))))))))))))))))))))))))
} s;
};
--
2.14.3
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