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Date:   Sat,  9 Dec 2017 16:59:14 +0300
From:   Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
To:     linux-snps-arc@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org,
        Vineet Gupta <Vineet.Gupta1@...opsys.com>,
        Alexey Brodkin <Alexey.Brodkin@...opsys.com>,
        Stephen Boyd <sboyd@...eaurora.org>,
        "robh+dt @ kernel . org" <robh+dt@...nel.org>,
        Eugeniy Paltsev <Eugeniy.Paltsev@...opsys.com>
Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS

Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.  
It will be applied at the core pll driver probing.

Eugeniy Paltsev (4):
  ARC: [plat-hsdk]: Set initial core pll output frequency
  ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
  ARC: [plat-axs103]: Set initial core pll output frequency
  ARC: [plat-axs103] refactor the quad core DT quirk code

 arch/arc/boot/dts/axc003.dtsi     |  3 +++
 arch/arc/boot/dts/axc003_idu.dtsi |  3 +++
 arch/arc/boot/dts/hsdk.dts        |  3 +++
 arch/arc/plat-axs10x/axs10x.c     | 18 ++++++++---------
 arch/arc/plat-hsdk/platform.c     | 42 ---------------------------------------
 5 files changed, 17 insertions(+), 52 deletions(-)

-- 
2.9.3

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