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Message-ID: <20171209001853.GK7997@codeaurora.org>
Date: Fri, 8 Dec 2017 16:18:53 -0800
From: Stephen Boyd <sboyd@...eaurora.org>
To: Abhishek Sahu <absahu@...eaurora.org>
Cc: Michael Turquette <mturquette@...libre.com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 04/13] clk: qcom: fix 16 bit alpha support calculation
On 09/28, Abhishek Sahu wrote:
> The alpha value calculation function has been written for 40 bit
> alpha which is not coming properly for 16 bit
>
> 1. Alpha value is being calculated on the basis of
> ALPHA_BITWIDTH to make the computation easy for 40 bit alpha.
> After calculating the 32 bit alpha, It is being converted to 40
> bit alpha by making making lower bits zero. But if actual alpha
> register width is less than ALPHA_BITWIDTH, then the actual width
> can be used for calculation
>
> 2. During 40 bit alpha pll set rate, the lower alpha register is
> not being configured
>
> Now the changes have been made to calculate the rate and register
> values from alpha_width instead hardcoding it so that it can work
> for all the cases.
>
> Signed-off-by: Abhishek Sahu <absahu@...eaurora.org>
> ---
Applied to clk-next
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