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Message-Id: <20171211075001.6100-3-mylene.josserand@free-electrons.com>
Date:   Mon, 11 Dec 2017 08:49:59 +0100
From:   Mylène Josserand 
        <mylene.josserand@...e-electrons.com>
To:     maxime.ripard@...e-electrons.com, wens@...e.org,
        linux@...linux.org.uk, robh+dt@...nel.org, mark.rutland@....com
Cc:     linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org, mylene.josserand@...e-electrons.com,
        thomas.petazzoni@...e-electrons.com
Subject: [PATCH 2/4] arm: dts: sun8i: a83t: Add registers needed for MCPM

Add 3 registers needed for MCPM (ie SMP): prcm, cpucfg and r_cpucfg.
prcm and cpucfg are identical with sun9i-a80. The only difference
is the r_cpucfg that does not exist on sun9i.

Signed-off-by: Mylène Josserand <mylene.josserand@...e-electrons.com>
---
 arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index a384b766f3dc..eeb2e7d0d6dc 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -323,6 +323,16 @@
 			#reset-cells = <1>;
 		};
 
+		cpucfg@...00000 {
+			compatible = "allwinner,sun9i-a80-cpucfg";
+			reg = <0x01700000 0x100>;
+		};
+
+		r_cpucfg@...1c00 {
+			compatible = "allwinner,sun8i-a83t-r-cpucfg";
+			reg = <0x1f01c00 0x100>;
+		};
+
 		pio: pinctrl@...0800 {
 			compatible = "allwinner,sun8i-a83t-pinctrl";
 			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
@@ -493,6 +503,11 @@
 			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		prcm@...1400 {
+			compatible = "allwinner,sun9i-a80-prcm";
+			reg = <0x1f01400 0x200>;
+		};
+
 		r_ccu: clock@...1400 {
 			compatible = "allwinner,sun8i-a83t-r-ccu";
 			reg = <0x01f01400 0x400>;
-- 
2.11.0

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