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Date:   Mon, 11 Dec 2017 10:45:59 +0000
From:   Mark Rutland <mark.rutland@....com>
To:     Shanker Donthineni <shankerd@...eaurora.org>
Cc:     Will Deacon <will.deacon@....com>,
        Marc Zyngier <marc.zyngier@....com>,
        linux-arm-kernel@...ts.infradead.org, linux-efi@...r.kernel.org,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        Matt Fleming <matt@...eblueprint.co.uk>,
        Catalin Marinas <catalin.marinas@....com>,
        linux-kernel@...r.kernel.org, Robin Murphy <robin.murphy@....com>,
        kvmarm@...ts.cs.columbia.edu
Subject: Re: [RESEND PATCH v4 2/2] arm64: Add software workaround for Falkor
 erratum 1041

Hi,

On Sun, Dec 10, 2017 at 08:03:43PM -0600, Shanker Donthineni wrote:
> +/**
> + * Errata workaround prior to disable MMU. Insert an ISB immediately prior
> + * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0.
> + */
> +	.macro pre_disable_mmu_workaround
> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
> +alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1041
> +	isb
> +alternative_else_nop_endif
> +#endif
> +	.endm

There's really no need for this to be an alternative. It makes the
kernel larger and more complex due to all the altinstr data and probing
code.

As Will suggested last time [1], please just use the ifdef, and always
compile-in the extra ISB if CONFIG_QCOM_FALKOR_ERRATUM_E1041 is
selected. Get rid of the alternatives and probing code.

All you need here is:

	/*
	 * Some Falkor parts make errant speculative instruction fetches
	 * when SCTLR_ELx.M is cleared. An ISB before the write to
	 * SCTLR_ELx prevents this.
	 */
	.macro pre_disable_mmu_workaround
#ifdef
	isb
#endif
	.endm

> +
> +	.macro pre_disable_mmu_early_workaround
> +#ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041
> +	isb
> +#endif
> +	.endm
> +

... and we don't need a special early variant.

Thanks,
Mark.

[1] https://lkml.kernel.org/r/20171201112457.GE18083@arm.com

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