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Message-ID: <1513112639.11361.0.camel@megha-Z97X-UD7-TH> Date: Tue, 12 Dec 2017 13:03:59 -0800 From: Megha Dey <megha.dey@...el.com> To: Jiri Olsa <jolsa@...hat.com> Cc: x86@...nel.org, linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org, tglx@...utronix.de, mingo@...hat.com, hpa@...or.com, andriy.shevchenko@...ux.intel.com, kstewart@...uxfoundation.org, yu-cheng.yu@...el.com, len.brown@...el.com, gregkh@...uxfoundation.org, peterz@...radead.org, acme@...nel.org, alexander.shishkin@...ux.intel.com, namhyung@...nel.org, vikas.shivappa@...ux.intel.com, pombredanne@...b.com, me@...ehuey.com, bp@...e.de, grzegorz.andrejczuk@...el.com, tony.luck@...el.com, corbet@....net, ravi.v.shankar@...el.com Subject: Re: [PATCH V2 2/3] perf/x86/intel/bm.c: Add Intel Branch Monitoring support On Mon, 2017-11-20 at 15:10 +0100, Jiri Olsa wrote: > On Fri, Nov 17, 2017 at 05:54:05PM -0800, Megha Dey wrote: > > SNIP > > > +/* Branch Monitoring default and mask values */ > > +#define BM_MAX_WINDOW_SIZE 0x3ff > > +#define BM_MAX_THRESHOLD 0x7f > > +#define BM_MAX_EVENTS 6 > > +#define BM_WINDOW_SIZE_SHIFT 8 > > +#define BM_THRESHOLD_SHIFT 8 > > +#define BM_EVENT_TYPE_SHIFT 1 > > +#define BM_GUEST_DISABLE_SHIFT 3 > > +#define BM_LBR_FREEZE_SHIFT 2 > > +#define BM_WINDOW_CNT_SEL_SHIFT 24 > > +#define BM_CNT_AND_MODE_SHIFT 26 > > +#define BM_MISPRED_EVT_CNT_SHIFT 15 > > +#define BM_ENABLE 0x3 > > +#define BM_CNTR_ENABLE 1 > > + > > +static unsigned int bm_window_size = BM_MAX_WINDOW_SIZE; > > +static unsigned int bm_guest_disable; > > +static unsigned int bm_lbr_freeze; > > +static unsigned int bm_window_cnt_sel; > > +static unsigned int bm_cnt_and_mode; > > + > > +static unsigned int bm_threshold = BM_MAX_THRESHOLD; > > +static unsigned int bm_mispred_evt_cnt; > > + > > +/* Branch monitoring counter owners */ > > +static struct perf_event **bm_counter_owner; > > that's still global.. 2 counters per system Yes, you are right . I will amend this in the next patch set. > > jirka
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