linux-kernel - Re: [PATCH v3 09/33] nds32: Cache and TLB routines

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Message-ID: <20171213021619.GA6254@gary-OptiPlex-3050>
Date:   Wed, 13 Dec 2017 10:16:20 +0800
From:   Guo Ren <ren_guo@...ky.com>
To:     Greentime Hu <green.hu@...il.com>
Cc:     greentime@...estech.com, linux-kernel@...r.kernel.org,
        arnd@...db.de, linux-arch@...r.kernel.org, tglx@...utronix.de,
        jason@...edaemon.net, marc.zyngier@....com, robh+dt@...nel.org,
        netdev@...r.kernel.org, deanbo422@...il.com,
        devicetree@...r.kernel.org, viro@...iv.linux.org.uk,
        dhowells@...hat.com, will.deacon@....com,
        daniel.lezcano@...aro.org, linux-serial@...r.kernel.org,
        geert.uytterhoeven@...il.com, linus.walleij@...aro.org,
        mark.rutland@....com, greg@...ah.com,
        Vincent Chen <vincentc@...estech.com>
Subject: Re: [PATCH v3 09/33] nds32: Cache and TLB routines

On Fri, Dec 08, 2017 at 05:11:52PM +0800, Greentime Hu wrote:
> From: Greentime Hu <greentime@...estech.com>
 [...]
> diff --git a/arch/nds32/mm/cacheflush.c b/arch/nds32/mm/cacheflush.c
 [...]
> +#ifndef CONFIG_CPU_CACHE_ALIASING
> +void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr,
> +		      pte_t * pte)
 [...]
> +	if (vma->vm_mm == current->active_mm) {
> +
> +		__nds32__mtsr_dsb(addr, NDS32_SR_TLB_VPN);
> +		__nds32__tlbop_rwr(*pte);
> +		__nds32__isb();
If there is an interruption between "mtsr_dsb" and "tlbop_rwr" and a
update_mmu_cache() is invoked again, then an error page mapping is
set up in your tlb-buffer when tlbop_rwr is excuted from interrupt.
Because it's another addr in NDS32_SR_TLB_VPN.

It seems that tlb-hardrefill can help build tlb-buffer mapping, why you
update it in this software way?

 Guo Ren