linux-kernel - [PATCH 2/2] MIPS: pm-cps: Warn if JTAG presence will block power gating

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Message-ID: <1513330494-21249-2-git-send-email-matt.redfearn@mips.com>
Date:   Fri, 15 Dec 2017 09:34:54 +0000
From:   Matt Redfearn <matt.redfearn@...s.com>
To:     Ralf Baechle <ralf@...ux-mips.org>, <jhogan@...nel.org>
CC:     <linux-mips@...ux-mips.org>,
        Matt Redfearn <matt.redfearn@...s.com>,
        Dengcheng Zhu <dengcheng.zhu@...s.com>,
        <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Paul Burton <paul.burton@...s.com>,
        Mark Rutland <mark.rutland@....com>
Subject: [PATCH 2/2] MIPS: pm-cps: Warn if JTAG presence will block power gating

If a JTAG probe is connected to a MIPS cluster, then the CPC detects it
and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set,
attempting to send a power-down command to a core will be blocked, and
the CPC will instead send the core to clock-off state. This can
interfere with systems fully entering a low power state where all cores,
CM, GIC, etc are powered down.

Detect that a JTAG probe is / has been connected to the cluster and emit
a warning that the attempted power down will fail, to aid debugging
system suspend where it is not currently obvious that a core has not
really powered down and will block a full power down of the cluster. We
use a ratelimited pr_warn since this path will also be hit by cpu idle
if it attempts to put cores into the powered down state.

Signed-off-by: Matt Redfearn <matt.redfearn@...s.com>
---

 arch/mips/kernel/pm-cps.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 421e06dfee72..45776613a5be 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -11,6 +11,7 @@
 #include <linux/cpuhotplug.h>
 #include <linux/init.h>
 #include <linux/percpu.h>
+#include <linux/ratelimit.h>
 #include <linux/slab.h>
 
 #include <asm/asm-offsets.h>
@@ -143,6 +144,18 @@ int cps_pm_enter_state(enum cps_pm_state state)
 
 	/* Setup the VPE to run mips_cps_pm_restore when started again */
 	if (IS_ENABLED(CONFIG_CPU_PM) && state == CPS_PM_POWER_GATED) {
+		unsigned int stat = read_cpc_cl_stat_conf();
+
+		if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
+			/*
+			 * If we're attempting to gate power to the core, the
+			 * JTAG detect bit indicates that the CPC will instead
+			 * put the core into clock-off state. Emit a warning.
+			 */
+			pr_warn_ratelimited("JTAG probe present - core%d will clock off instead of powering down\n",
+					    core);
+		}
+
 		/* Power gating relies upon CPS SMP */
 		if (!mips_cps_smp_in_use())
 			return -EINVAL;
-- 
2.7.4