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Message-ID: <87tvwpq63n.wl%kuninori.morimoto.gx@renesas.com>
Date:   Sun, 17 Dec 2017 23:46:29 +0000
From:   Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
Cc:     Laurent Pinchart <laurent.pinchart@...asonboard.com>,
        David Airlie <airlied@...ux.ie>,
        DRI Development <dri-devel@...ts.freedesktop.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 2/2] drm: rcar-du: calculate DPLLCR to be more small jitter


Hi Geert

> >> > From: Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>
> >> > In general, PLL has VCO (= Voltage controlled oscillator),
> >> > one of the very important electronic feature called as "jitter"
> >> > is related to this VCO.
> >> > In academic generalism, VCO should be maximum to be more small jitter.
> >> > In high frequency clock, jitter will be large impact.
> >> > Thus, selecting Hi VCO is general theory.
> >>
> >> Thanks for your patch!
> >>
> >> > One note here is that it should be 2000 < fvco < 4096MHz
> >>
> >> 2000 Hz? (else it could be misinterpreted that MHz applies to both values).
> >
> > Laurent had asked same question ;)
> > But, yes, it is 2000 Hz
> 
> I've seen his question, that's why I think you should make it unambiguous.

Ahh... OK yes indeed
will fix in v4

Best regards
---
Kuninori Morimoto

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