linux-kernel - [PATCH] KVM: x86: Assign separate names for Intel and AMD to LBR MSRs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [day] [month] [year] [list]

Message-Id: <20171217122230.b0309c5d5fac320d9a523b54@m.soramichi.jp>
Date:   Sun, 17 Dec 2017 12:22:30 +0900
From:   Soramichi AKIYAMA <akiyama@...oramichi.jp>
To:     linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
        tglx@...utronix.de, mingo@...hat.com, hpa@...or.com,
        pbonzini@...hat.com, rkrcmar@...hat.com
Subject: [PATCH] KVM: x86: Assign separate names for Intel and AMD to LBR
 MSRs

Some of the MSRs related to LBR (Last Branch Record) have different names
and layouts among Intel and AMD, but the kernel does not distinguish them.
Currently it does not invoke any bugs, but it is better to assign them separate
macros in order to avoid confusion.

Signed-off-by: Soramichi Akiyama <akiyama@...oramichi.jp>
---
 arch/x86/include/asm/msr-index.h | 19 +++++++++++++++----
 arch/x86/kvm/x86.c               |  8 ++++----
 2 files changed, 19 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 34c4922bbc3f..a1c69de453d1 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -123,10 +123,21 @@
 #define MSR_IA32_CR_PAT			0x00000277
 
 #define MSR_IA32_DEBUGCTLMSR		0x000001d9
-#define MSR_IA32_LASTBRANCHFROMIP	0x000001db
-#define MSR_IA32_LASTBRANCHTOIP		0x000001dc
-#define MSR_IA32_LASTINTFROMIP		0x000001dd
-#define MSR_IA32_LASTINTTOIP		0x000001de
+/*
+ * 0x1db - 0x1de have different names and layouts between Intel and AMD
+ * so it is better to define dedicated macros for each of them.
+ * An Intel one (e.g. MSR_IA32_LASTBRANCH0) contains both "from" and "to"
+ * addresses (because they are used only in old 32 bit CPUs), while an AMD
+ * one (e.g. MSR_IA32_LASTBRANCHFROMIP) contains only one 64 bits address.
+ */
+#define MSR_IA32_LASTBRANCH0		0x000001db /* Intel */
+#define MSR_IA32_LASTBRANCH1		0x000001dc /* Intel */
+#define MSR_IA32_LASTBRANCH2		0x000001dd /* Intel */
+#define MSR_IA32_LASTBRANCH3		0x000001de /* Intel */
+#define MSR_IA32_LASTBRANCHFROMIP	0x000001db /* AMD */
+#define MSR_IA32_LASTBRANCHTOIP		0x000001dc /* AMD */
+#define MSR_IA32_LASTINTFROMIP		0x000001dd /* AMD */
+#define MSR_IA32_LASTINTTOIP		0x000001de /* AMD */
 
 /* DEBUGCTLMSR bits (others vary by model): */
 #define DEBUGCTLMSR_LBR			(1UL <<  0) /* last branch recording */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 56d036b9ad75..cef109f112f5 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -2434,10 +2434,10 @@ int kvm_get_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
 	case MSR_IA32_PLATFORM_ID:
 	case MSR_IA32_EBL_CR_POWERON:
 	case MSR_IA32_DEBUGCTLMSR:
-	case MSR_IA32_LASTBRANCHFROMIP:
-	case MSR_IA32_LASTBRANCHTOIP:
-	case MSR_IA32_LASTINTFROMIP:
-	case MSR_IA32_LASTINTTOIP:
+	case MSR_IA32_LASTBRANCH0:
+	case MSR_IA32_LASTBRANCH1:
+	case MSR_IA32_LASTBRANCH2:
+	case MSR_IA32_LASTBRANCH3:
 	case MSR_K8_SYSCFG:
 	case MSR_K8_TSEG_ADDR:
 	case MSR_K8_TSEG_MASK:
-- 
2.11.0