linux-kernel - [PATCH 4.9 137/177] clk: hi6220: mark clock cs_atb

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Message-Id: <20171218152917.089108951@linuxfoundation.org>
Date:   Mon, 18 Dec 2017 16:49:20 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Guodong Xu <guodong.xu@...aro.org>,
        Zhangfei Gao <zhangfei.gao@...aro.org>,
        Haojian Zhuang <haojian.zhuang@...aro.org>,
        Leo Yan <leo.yan@...aro.org>,
        Michael Turquette <mturquette@...libre.com>,
        Sasha Levin <alexander.levin@...izon.com>
Subject: [PATCH 4.9 137/177] clk: hi6220: mark clock cs_atb_syspll as critical

4.9-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Leo Yan <leo.yan@...aro.org>


[ Upstream commit d2a3671ebe6479483a12f94fcca63c058d95ad64 ]

Clock cs_atb_syspll is pll used for coresight trace bus; when clock
cs_atb_syspll is disabled and operates its child clock node cs_atb
results in system hang. So mark clock cs_atb_syspll as critical to
keep it enabled.

Cc: Guodong Xu <guodong.xu@...aro.org>
Cc: Zhangfei Gao <zhangfei.gao@...aro.org>
Cc: Haojian Zhuang <haojian.zhuang@...aro.org>
Signed-off-by: Leo Yan <leo.yan@...aro.org>
Signed-off-by: Michael Turquette <mturquette@...libre.com>
Link: lkml.kernel.org/r/1504226835-2115-2-git-send-email-leo.yan@...aro.org
Signed-off-by: Sasha Levin <alexander.levin@...izon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 drivers/clk/hisilicon/clk-hi6220.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/drivers/clk/hisilicon/clk-hi6220.c
+++ b/drivers/clk/hisilicon/clk-hi6220.c
@@ -144,7 +144,7 @@ static struct hisi_gate_clock hi6220_sep
 	{ HI6220_BBPPLL_SEL,    "bbppll_sel",    "pll0_bbp_gate",  CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 9,  0, },
 	{ HI6220_MEDIA_PLL_SRC, "media_pll_src", "pll_media_gate", CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 10, 0, },
 	{ HI6220_MMC2_SEL,      "mmc2_sel",      "mmc2_mux1",      CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 11, 0, },
-	{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IGNORE_UNUSED, 0x270, 12, 0, },
+	{ HI6220_CS_ATB_SYSPLL, "cs_atb_syspll", "syspll",         CLK_SET_RATE_PARENT|CLK_IS_CRITICAL,   0x270, 12, 0, },
 };
 
 static struct hisi_mux_clock hi6220_mux_clks_sys[] __initdata = {