linux-kernel - [PATCH 0/2] ti-pipe3: PCIe x2 lane mode configuration in dra72

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Message-ID: <20171219094540.18432-1-kishon@ti.com>
Date:   Tue, 19 Dec 2017 15:15:38 +0530
From:   Kishon Vijay Abraham I <kishon@...com>
To:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>, <kishon@...com>
CC:     <devicetree@...r.kernel.org>, <linux-pci@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>, <nsekhar@...com>
Subject: [PATCH 0/2] ti-pipe3: PCIe x2 lane mode configuration in dra72

DRA72 uses the same pipe3 PHY for the 2nd lane of PCIE and USB3 PHY.
By default it is configured to be used as USB3 PHY and some special
configuration has to be done inorder to use it for the 2nd lane of PCIE.

This series adds a new dt property and the configuration required to
enable 2nd lane of PCIE.

Kishon Vijay Abraham I (2):
  dt-bindings: phy: ti-pipe3: Add dt binding to use USB3 PHY for PCIe
  phy: ti-pipe3: configure usb3 phy to be used as pcie phy

 Documentation/devicetree/bindings/phy/ti-phy.txt |  2 +
 drivers/phy/ti/phy-ti-pipe3.c                    | 47 +++++++++++++++++++++---
 2 files changed, 43 insertions(+), 6 deletions(-)

-- 
2.11.0