[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20171219095250.38757-2-yinbo.zhu@nxp.com>
Date: Tue, 19 Dec 2017 17:52:49 +0800
From: <yinbo.zhu@....com>
To: Felipe Balbi <balbi@...com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Mathias Nyman <mathias.nyman@...el.com>,
"open list:DESIGNWARE USB3 DRD IP DRIVER" <linux-usb@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>
CC: <xiaobo.xie@....com>, <jerry.huang@....com>, <ran.wang_1@....com>,
"yinbo . zhu" <yinbo.zhu@....com>
Subject: [PATCH v3 2/3] usb: host: Implement workaround for Erratum A-009611
From: yinbo.zhu <yinbo.zhu@....com>
This is a occasional problem where the software issues an End
Transfer command while a USB transfer is in progress,
resulting in the TxFIFO being flushed when the lower layer is
waiting for data, causing the super speed (ss) transmit to get
blocked. If the End Transfer command is issued on an IN
endpoint to flush out the pending transfers when the same IN
endpoint is doing transfers on the USB, then depending upon
the timing of the End Transfer (and the resulting internal
flush),the lower layer (U3PTL/U3MAC) could get stuck waiting
for data indefinitely. This blocks the transmission path on
the SS, and no DP/ACK/ERDY/DEVNOTIF packets can be sent from
the device. Impact: If this issue happens and the transmission
gets blocked, then the USB host aborts and
resets/re-enumerates the device. This unblocks the transmitt
engine and the device functions normally.
Workaround: Software must wait for all existing TRBs to
complete before issuing End transfer command.
Configs Affected:
LS1088-48A-R1.0, LS2081A-R1.1, LS2088-48A-R1.0,
LS2088-48A-R1.1, LX2160-2120-2080A-R1.
Signed-off-by: yinbo.zhu <yinbo.zhu@....com>
---
Change in v3:
Adjust the commit information.
Replace "(1<<33)" with BIT(33).
Update the DT properity description.
Update erratum description in code comment.
drivers/usb/dwc3/core.c | 2 ++
drivers/usb/dwc3/core.h | 3 +++
drivers/usb/dwc3/host.c | 3 +++
drivers/usb/host/xhci-plat.c | 4 ++++
drivers/usb/host/xhci.c | 25 +++++++++++++++++++------
drivers/usb/host/xhci.h | 1 +
6 files changed, 32 insertions(+), 6 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 6613bc0..863f2c0 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1057,6 +1057,8 @@ static void dwc3_get_properties(struct dwc3 *dwc)
"snps,tx_de_emphasis_quirk");
dwc->quirk_reverse_in_out = device_property_read_bool(dev,
"snps,quirk_reverse_in_out");
+ dwc->quirk_stop_transfer_in_block = device_property_read_bool(dev,
+ "snps,quirk_stop_transfer_in_block");
device_property_read_u8(dev, "snps,tx_de_emphasis",
&tx_de_emphasis);
device_property_read_string(dev, "snps,hsphy_interface",
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index a263fdc..6276678 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -858,6 +858,8 @@ struct dwc3_scratchpad_array {
* 2 - No de-emphasis
* 3 - Reserved
* @quirk_reverse_in_out: prevent tx fifo reverse the data direction
+ * @quirk_stop_transfer_in_block: prevent block transmission from being
+ * interrupted
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
*/
@@ -1011,6 +1013,7 @@ struct dwc3 {
unsigned tx_de_emphasis_quirk:1;
unsigned tx_de_emphasis:2;
unsigned quirk_reverse_in_out:1;
+ unsigned quirk_stop_transfer_in_block:1;
u16 imod_interval;
};
diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c
index dab5f49..78cb7bb 100644
--- a/drivers/usb/dwc3/host.c
+++ b/drivers/usb/dwc3/host.c
@@ -93,6 +93,9 @@ int dwc3_host_init(struct dwc3 *dwc)
if (dwc->quirk_reverse_in_out)
props[prop_idx++].name = "quirk-reverse-in-out";
+ if (dwc->quirk_stop_transfer_in_block)
+ props[prop_idx++].name = "quirk-stop-transfer-in-block";
+
if (dwc->usb3_lpm_capable)
props[prop_idx++].name = "usb3-lpm-capable";
diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index fe71b92..35e0fc8 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -269,6 +269,10 @@ static int xhci_plat_probe(struct platform_device *pdev)
if (device_property_read_bool(&pdev->dev, "quirk-reverse-in-out"))
xhci->quirks |= XHCI_REVERSE_IN_OUT;
+ if (device_property_read_bool(&pdev->dev,
+ "quirk-stop-transfer-in-block"))
+ xhci->quirks |= XHCI_STOP_TRANSFER_IN_BLOCK;
+
if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
xhci->quirks |= XHCI_BROKEN_PORT_PED;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 05104bd..5141856 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -1501,13 +1501,26 @@ static int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
ret = -ENOMEM;
goto done;
}
- ep->ep_state |= EP_STOP_CMD_PENDING;
- ep->stop_cmd_timer.expires = jiffies +
+ /*
+ *erratum A-009611: Issuing an End Transfer command on an IN
+ *endpoint. when a transfer is in progress on USB blocks the
+ *transmission.
+ *Workaround: Software must wait for all existing TRBs to
+ *complete before issuing End transfer command.
+ */
+ if ((ep_ring->enqueue == ep_ring->dequeue &&
+ (xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) ||
+ !(xhci->quirks & XHCI_STOP_TRANSFER_IN_BLOCK)) {
+ ep->ep_state |= EP_STOP_CMD_PENDING;
+ ep->stop_cmd_timer.expires = jiffies +
XHCI_STOP_EP_CMD_TIMEOUT * HZ;
- add_timer(&ep->stop_cmd_timer);
- xhci_queue_stop_endpoint(xhci, command, urb->dev->slot_id,
- ep_index, 0);
- xhci_ring_cmd_db(xhci);
+ add_timer(&ep->stop_cmd_timer);
+ xhci_queue_stop_endpoint(xhci, command,
+ urb->dev->slot_id,
+ ep_index, 0);
+ xhci_ring_cmd_db(xhci);
+ }
+
}
done:
spin_unlock_irqrestore(&xhci->lock, flags);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 9f133a9..db10ee4 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1820,6 +1820,7 @@ struct xhci_hcd {
#define XHCI_NO_64BIT_SUPPORT (1 << 23)
#define XHCI_MISSING_CAS (1 << 24)
#define XHCI_REVERSE_IN_OUT BIT(32)
+#define XHCI_STOP_TRANSFER_IN_BLOCK BIT(33)
/* For controller with a broken Port Disable implementation */
#define XHCI_BROKEN_PORT_PED (1 << 25)
#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 (1 << 26)
--
1.7.1
Powered by blists - more mailing lists