lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Wed, 20 Dec 2017 19:26:51 +0300
From:   Jan Dakinevich <jan.dakinevich@...tuozzo.com>
To:     <linux-kernel@...r.kernel.org>
Cc:     "Denis V . Lunev" <den@...tuozzo.com>,
        Roman Kagan <rkagan@...tuozzo.com>,
        Peter Zijlstra <peterz@...radead.org>,
        Ingo Molnar <mingo@...hat.com>,
        Arnaldo Carvalho de Melo <acme@...nel.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Namhyung Kim <namhyung@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>, <x86@...nel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Andi Kleen <ak@...ux.intel.com>,
        Kan Liang <kan.liang@...el.com>,
        Colin King <colin.king@...onical.com>,
        Stephane Eranian <eranian@...gle.com>,
        Sebastian Andrzej Siewior <bigeasy@...utronix.de>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Jin Yao <yao.jin@...ux.intel.com>, <kvm@...r.kernel.org>
Subject: Re: [PATCH RFC 0/2] ignore LBR-related MSRs

On Wed, 6 Dec 2017 14:43:01 +0300
Jan Dakinevich <jan.dakinevich@...tuozzo.com> wrote:

> w2k16 essentials fails to boot if underlying hypervisor lacks of
> support for LBR MSRs. To workaround the issue, it suggessted to
> ignore these MSRs (but not all).
> 
> The information, which MSRs are supported for specific platform is
> taken from perf, it is the subject of the first patch. The second
> patch adds ignoring for these MSRs to pmu_intel code of KVM.
> 
> TODO: use MSR load/store areas to make full support of LBR debug.
> 
> Jan Dakinevich (2):
>   perf/x86/intel: make reusable LBR initialization code
>   KVM: x86/vPMU: ignore access to LBR-related MSRs
> 
>  arch/x86/events/core.c            |   8 +-
>  arch/x86/events/intel/core.c      |  59 +++------
>  arch/x86/events/intel/lbr.c       | 272
> +++++++++++++++++++++++++-------------
> arch/x86/events/perf_event.h      |  27 +---
> arch/x86/include/asm/kvm_host.h   |   2 +
> arch/x86/include/asm/perf_event.h |  11 ++
> arch/x86/kvm/pmu_intel.c          |  33 +++++ 7 files changed, 250
> insertions(+), 162 deletions(-)
> 

ping

Please, tell me whether these patches are applicable (as KVM workaround)
or it is assumed they should be reworked following to recommendation by
Andi Kleen?

-- 
Best regards
Jan Dakinevich

Powered by blists - more mailing lists