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Message-Id: <20171220192702.32515-2-krzk@kernel.org> Date: Wed, 20 Dec 2017 20:27:02 +0100 From: Krzysztof Kozlowski <krzk@...nel.org> To: Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will.deacon@....com>, Kukjin Kim <kgene@...nel.org>, Krzysztof Kozlowski <krzk@...nel.org>, Chanwoo Choi <cw00.choi@...sung.com>, Marek Szyprowski <m.szyprowski@...sung.com>, Andrzej Hajda <a.hajda@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH 2/2] arm64: dts: exynos: Fix typo in MSCL clock controller unit address Fix typo in unit address of MSCL clock controller (the reg entry is correct). Signed-off-by: Krzysztof Kozlowski <krzk@...nel.org> --- arch/arm64/boot/dts/exynos/exynos5433.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi index 0ba5df825eff..3e8311c60d1b 100644 --- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi @@ -468,7 +468,7 @@ clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>; }; - cmu_mscl: clock-controller@...d0000 { + cmu_mscl: clock-controller@...d0000 { compatible = "samsung,exynos5433-cmu-mscl"; reg = <0x150d0000 0x1000>; #clock-cells = <1>; -- 2.11.0
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