linux-kernel - [PATCH 3/4] iommu/vt-d: Add a check for 5-level paging support

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Message-Id: <1513799967-22454-4-git-send-email-sohil.mehta@intel.com>
Date:   Wed, 20 Dec 2017 11:59:26 -0800
From:   Sohil Mehta <sohil.mehta@...el.com>
To:     Joerg Roedel <joro@...tes.org>,
        Alex Williamson <alex.williamson@...hat.com>
Cc:     David Woodhouse <dwmw2@...radead.org>,
        Ashok Raj <ashok.raj@...el.com>,
        iommu@...ts.linux-foundation.org, linux-kernel@...r.kernel.org,
        Jacob Pan <jacob.jun.pan@...ux.intel.com>,
        Gayatri Kammela <gayatri.kammela@...el.com>,
        Sohil Mehta <sohil.mehta@...el.com>,
        Ravi V Shankar <ravi.v.shankar@...el.com>,
        Andy Shevchenko <andriy.shevchenko@...el.com>,
        Lu Baolu <baolu.lu@...ux.intel.com>,
        Fenghua Yu <fenghua.yu@...el.com>,
        Kirill Shutemov <kirill.shutemov@...ux.intel.com>,
        Dave Hansen <dave.hansen@...el.com>
Subject: [PATCH 3/4] iommu/vt-d: Add a check for 5-level paging support

Add a check to verify IOMMU 5-level paging support. If the CPU supports
supports 5-level paging but the IOMMU does not support it then disable
SVM by not allocating PASID tables.

Signed-off-by: Sohil Mehta <sohil.mehta@...el.com>
---
 drivers/iommu/intel-svm.c   | 4 ++++
 include/linux/intel-iommu.h | 1 +
 2 files changed, 5 insertions(+)

diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c
index fcab440..4072a18 100644
--- a/drivers/iommu/intel-svm.c
+++ b/drivers/iommu/intel-svm.c
@@ -45,6 +45,10 @@ int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
 			!cap_fl1gp_support(iommu->cap))
 		return -EINVAL;
 
+	if (cpu_feature_enabled(X86_FEATURE_LA57) &&
+			!cap_5lp_support(iommu->cap))
+		return -EINVAL;
+
 	/* Start at 2 because it's defined as 2^(1+PSS) */
 	iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
 
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
index a56bab1..8dad3dd 100644
--- a/include/linux/intel-iommu.h
+++ b/include/linux/intel-iommu.h
@@ -83,6 +83,7 @@
 /*
  * Decoding Capability Register
  */
+#define cap_5lp_support(c)	(((c) >> 60) & 1)
 #define cap_pi_support(c)	(((c) >> 59) & 1)
 #define cap_fl1gp_support(c)	(((c) >> 56) & 1)
 #define cap_read_drain(c)	(((c) >> 55) & 1)
-- 
2.7.4