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Date:   Thu, 21 Dec 2017 11:16:04 +0000
From:   Matt Redfearn <>
To:     Ralf Baechle <>, James Hogan <>
CC:     <>,
        Matt Redfearn <>,
        "Paul Burton" <>,
        James Hogan <>,
        "stable # v4 . 9+" <>,
        Huacai Chen <>, <>
Subject: [PATCH 3/3] MIPS: Add barrier between icache flush and execution hazard barrier

Hit-based icache operations may complete before the CM completes
intervention with the local L1. Thus code which invalidates the icache
and then attempts to execute those addresses must include a barrier to
prevent the scenario which:

  - icache instruction completes
  - icache fetch occurs
  - core executes icache data
  - CM completes icache invalidate

If the above were allowed to happen then the core would execute stale
instructions from the icache.

A barrier is required to prevent the core i-fetching before the icache
operation has completed. This goes together with the instruction_hazard
to ensure that the pipeline is stalled until the icache operation is
completed and the core will fetch the new instructions.

Suggested-by: Leonid Yegoshin <>
Signed-off-by: Matt Redfearn <>
Cc: Paul Burton <>
Cc: James Hogan <>
Cc: stable <> # v4.9+

 arch/mips/mm/c-r4k.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index b7186d47184b..844685e51109 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -763,6 +763,8 @@ static inline void __local_r4k_flush_icache_range(unsigned long start,
+	/* Ensure icache operation has completed */
+	mb();
 	/* Hazard to force new i-fetch */

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