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Date:   Fri, 22 Dec 2017 12:19:03 +1300
From:   Chris Packham <chris.packham@...iedtelesis.co.nz>
To:     ezequiel.garcia@...e-electrons.com,
        boris.brezillon@...e-electrons.com, richard@....at,
        dwmw2@...radead.org, computersforpeace@...il.com,
        marek.vasut@...il.com, cyrille.pitchen@...ev4u.fr,
        miquel.raynal@...e-electrons.com, linux-mtd@...ts.infradead.org
Cc:     linux-kernel@...r.kernel.org,
        Chris Packham <chris.packham@...iedtelesis.co.nz>
Subject: [PATCHv4 0/1] Set FORCE_CSX bit when arbitration between NAND and NOR is enabled

Note: I've picked this up from Kalyan to try and get things into shape for
submission upstream.

When the arbitration between NOR and NAND flash is enabled
the <FORCE_CSX> field bit[21] in the Data Flash Control Register
needs to be set to 1 according to guidleine GL-5830741
mentioned in Marvell Errata document MV-S501377-00, Rev. D.

Set the FORCE_CSX bit in NDCR for ARMADA370 variants as the arbitration
is always enabled by default. This change does not apply for pxa3xx
variants because FORCE_CSX bit does not exist/reserved on the NFCv1.

Ran the "flash_speed" tool on NAND flash on a board with
Armada-xp based SoC which uses only one NAND chip and not using
the arbiter. There is no regression or speed penalty
introduced due to this change.

Kalyan Kinthada (1):
  mtd: nand: pxa3xx: Set FORCE_CSX bit to ARMADA370 variants

 drivers/mtd/nand/pxa3xx_nand.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

-- 
2.15.1

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