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Message-ID: <alpine.DEB.2.20.1712291434110.1899@nanos>
Date:   Fri, 29 Dec 2017 14:35:38 +0100 (CET)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     mingo@...nel.org, pavel@....cz, hpa@...or.com,
        linux-kernel@...r.kernel.org
cc:     linux-tip-commits@...r.kernel.org
Subject: Re: [tip:x86/urgent] x86/apic: Switch all APICs to Fixed delivery
 mode

On Fri, 29 Dec 2017, tip-bot for Thomas Gleixner wrote:

> Commit-ID:  a31e58e129f73ab5b04016330b13ed51fde7a961
> Gitweb:     https://git.kernel.org/tip/a31e58e129f73ab5b04016330b13ed51fde7a961
> Author:     Thomas Gleixner <tglx@...utronix.de>
> AuthorDate: Thu, 28 Dec 2017 11:33:33 +0100
> Committer:  Thomas Gleixner <tglx@...utronix.de>
> CommitDate: Fri, 29 Dec 2017 14:20:48 +0100
> 
> x86/apic: Switch all APICs to Fixed delivery mode

Note, the patch itself is unchanged. I merily amended the change log to
point out that fixed delivery mode is already used on this kind of systems
so the risk of this change is very low.

Thanks,

	tglx

> Some of the APIC incarnations are operating in lowest priority delivery
> mode. This worked as long as the vector management code allocated the same
> vector on all possible CPUs for each interrupt.
> 
> Lowest priority delivery mode does not necessarily respect the affinity
> setting and may redirect to some other online CPU. This was documented
> somewhere in the old code and the conversion to single target delivery
> missed to update the delivery mode of the affected APIC drivers which
> results in spurious interrupts on some of the affected CPU/Chipset
> combinations.
> 
> Switch the APIC drivers over to Fixed delivery mode and remove all
> leftovers of lowest priority delivery mode.
> 
> Switching to Fixed delivery mode is not a problem on these CPUs because the
> kernel already uses Fixed delivery mode for IPIs. The reason for this is
> that th SDM explicitely forbids lowest prio mode for IPIs. The reason is
> obvious: If the irq routing does not honor destination targets in lowest
> prio mode then an IPI targeted at CPU1 might end up on CPU0, which would be
> a fatal problem in many cases.
> 
> As a consequence of this change, the apic::irq_delivery_mode field is now
> pointless, but this needs to be cleaned up in a separate patch.
> 
> Fixes: fdba46ffb4c2 ("x86/apic: Get rid of multi CPU affinity")
> Reported-by: vcaputo@...garu.com
> Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
> Tested-by: vcaputo@...garu.com
> Cc: Pavel Machek <pavel@....cz>
> Link: https://lkml.kernel.org/r/alpine.DEB.2.20.1712281140440.1688@nanos
> ---
>  arch/x86/kernel/apic/apic_flat_64.c   | 2 +-
>  arch/x86/kernel/apic/apic_noop.c      | 2 +-
>  arch/x86/kernel/apic/msi.c            | 8 ++------
>  arch/x86/kernel/apic/probe_32.c       | 2 +-
>  arch/x86/kernel/apic/x2apic_cluster.c | 2 +-
>  drivers/pci/host/pci-hyperv.c         | 8 ++------
>  6 files changed, 8 insertions(+), 16 deletions(-)
> 
> diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
> index aa85690..25a8702 100644
> --- a/arch/x86/kernel/apic/apic_flat_64.c
> +++ b/arch/x86/kernel/apic/apic_flat_64.c
> @@ -151,7 +151,7 @@ static struct apic apic_flat __ro_after_init = {
>  	.apic_id_valid			= default_apic_id_valid,
>  	.apic_id_registered		= flat_apic_id_registered,
>  
> -	.irq_delivery_mode		= dest_LowestPrio,
> +	.irq_delivery_mode		= dest_Fixed,
>  	.irq_dest_mode			= 1, /* logical */
>  
>  	.disable_esr			= 0,
> diff --git a/arch/x86/kernel/apic/apic_noop.c b/arch/x86/kernel/apic/apic_noop.c
> index 7b659c4..5078b5c 100644
> --- a/arch/x86/kernel/apic/apic_noop.c
> +++ b/arch/x86/kernel/apic/apic_noop.c
> @@ -110,7 +110,7 @@ struct apic apic_noop __ro_after_init = {
>  	.apic_id_valid			= default_apic_id_valid,
>  	.apic_id_registered		= noop_apic_id_registered,
>  
> -	.irq_delivery_mode		= dest_LowestPrio,
> +	.irq_delivery_mode		= dest_Fixed,
>  	/* logical delivery broadcast to all CPUs: */
>  	.irq_dest_mode			= 1,
>  
> diff --git a/arch/x86/kernel/apic/msi.c b/arch/x86/kernel/apic/msi.c
> index 9b18be7..ce503c9 100644
> --- a/arch/x86/kernel/apic/msi.c
> +++ b/arch/x86/kernel/apic/msi.c
> @@ -39,17 +39,13 @@ static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
>  		((apic->irq_dest_mode == 0) ?
>  			MSI_ADDR_DEST_MODE_PHYSICAL :
>  			MSI_ADDR_DEST_MODE_LOGICAL) |
> -		((apic->irq_delivery_mode != dest_LowestPrio) ?
> -			MSI_ADDR_REDIRECTION_CPU :
> -			MSI_ADDR_REDIRECTION_LOWPRI) |
> +		MSI_ADDR_REDIRECTION_CPU |
>  		MSI_ADDR_DEST_ID(cfg->dest_apicid);
>  
>  	msg->data =
>  		MSI_DATA_TRIGGER_EDGE |
>  		MSI_DATA_LEVEL_ASSERT |
> -		((apic->irq_delivery_mode != dest_LowestPrio) ?
> -			MSI_DATA_DELIVERY_FIXED :
> -			MSI_DATA_DELIVERY_LOWPRI) |
> +		MSI_DATA_DELIVERY_FIXED |
>  		MSI_DATA_VECTOR(cfg->vector);
>  }
>  
> diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
> index fa22017..02e8acb 100644
> --- a/arch/x86/kernel/apic/probe_32.c
> +++ b/arch/x86/kernel/apic/probe_32.c
> @@ -105,7 +105,7 @@ static struct apic apic_default __ro_after_init = {
>  	.apic_id_valid			= default_apic_id_valid,
>  	.apic_id_registered		= default_apic_id_registered,
>  
> -	.irq_delivery_mode		= dest_LowestPrio,
> +	.irq_delivery_mode		= dest_Fixed,
>  	/* logical delivery broadcast to all CPUs: */
>  	.irq_dest_mode			= 1,
>  
> diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
> index 622f13c..8b04234 100644
> --- a/arch/x86/kernel/apic/x2apic_cluster.c
> +++ b/arch/x86/kernel/apic/x2apic_cluster.c
> @@ -184,7 +184,7 @@ static struct apic apic_x2apic_cluster __ro_after_init = {
>  	.apic_id_valid			= x2apic_apic_id_valid,
>  	.apic_id_registered		= x2apic_apic_id_registered,
>  
> -	.irq_delivery_mode		= dest_LowestPrio,
> +	.irq_delivery_mode		= dest_Fixed,
>  	.irq_dest_mode			= 1, /* logical */
>  
>  	.disable_esr			= 0,
> diff --git a/drivers/pci/host/pci-hyperv.c b/drivers/pci/host/pci-hyperv.c
> index 0fe3ea1..e7d9447 100644
> --- a/drivers/pci/host/pci-hyperv.c
> +++ b/drivers/pci/host/pci-hyperv.c
> @@ -985,9 +985,7 @@ static u32 hv_compose_msi_req_v1(
>  	int_pkt->wslot.slot = slot;
>  	int_pkt->int_desc.vector = vector;
>  	int_pkt->int_desc.vector_count = 1;
> -	int_pkt->int_desc.delivery_mode =
> -		(apic->irq_delivery_mode == dest_LowestPrio) ?
> -			dest_LowestPrio : dest_Fixed;
> +	int_pkt->int_desc.delivery_mode = dest_Fixed;
>  
>  	/*
>  	 * Create MSI w/ dummy vCPU set, overwritten by subsequent retarget in
> @@ -1008,9 +1006,7 @@ static u32 hv_compose_msi_req_v2(
>  	int_pkt->wslot.slot = slot;
>  	int_pkt->int_desc.vector = vector;
>  	int_pkt->int_desc.vector_count = 1;
> -	int_pkt->int_desc.delivery_mode =
> -		(apic->irq_delivery_mode == dest_LowestPrio) ?
> -			dest_LowestPrio : dest_Fixed;
> +	int_pkt->int_desc.delivery_mode = dest_Fixed;
>  
>  	/*
>  	 * Create MSI w/ dummy vCPU set targeting just one vCPU, overwritten
> 

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