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Message-Id: <1514533978-20408-16-git-send-email-zhengsq@rock-chips.com>
Date: Fri, 29 Dec 2017 15:52:57 +0800
From: Shunqian Zheng <zhengsq@...k-chips.com>
To: linux-rockchip@...ts.infradead.org, linux-media@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
mchehab@...nel.org, sakari.ailus@...ux.intel.com,
hans.verkuil@...co.com, tfiga@...omium.org, zhengsq@...k-chips.com,
laurent.pinchart@...asonboard.com, zyc@...k-chips.com,
eddie.cai.linux@...il.com, jeffy.chen@...k-chips.com,
allon.huang@...k-chips.com, devicetree@...r.kernel.org,
heiko@...ech.de, robh+dt@...nel.org, Joao.Pinto@...opsys.com,
Luis.Oliveira@...opsys.com, Jose.Abreu@...opsys.com,
jacob2.chen@...k-chips.com
Subject: [PATCH v5 15/16] arm64: dts: rockchip: add rx0 mipi-phy for rk3399
It's a Designware MIPI D-PHY, used for ISP0 in rk3399.
Signed-off-by: Shunqian Zheng <zhengsq@...k-chips.com>
Signed-off-by: Jacob Chen <jacob2.chen@...k-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 66a912f..8ef321f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1292,6 +1292,16 @@
status = "disabled";
};
+ mipi_dphy_rx0: mipi-dphy-rx0 {
+ compatible = "rockchip,rk3399-mipi-dphy";
+ clocks = <&cru SCLK_MIPIDPHY_REF>,
+ <&cru SCLK_DPHY_RX0_CFG>,
+ <&cru PCLK_VIO_GRF>;
+ clock-names = "dphy-ref", "dphy-cfg", "grf";
+ power-domains = <&power RK3399_PD_VIO>;
+ status = "disabled";
+ };
+
u2phy0: usb2-phy@...0 {
compatible = "rockchip,rk3399-usb2phy";
reg = <0xe450 0x10>;
--
1.9.1
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