linux-kernel - [PATCH 32/33] clk: lpc32xx: change round

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Message-Id: <1514596392-22270-33-git-send-email-pure.logic@nexus-software.ie>
Date:   Sat, 30 Dec 2017 01:13:11 +0000
From:   Bryan O'Donoghue <pure.logic@...us-software.ie>
To:     mturquette@...libre.com, sboyd@...eaurora.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Cc:     pure.logic@...us-software.ie, Vladimir Zapolskiy <vz@...ia.com>,
        Sylvain Lemieux <slemieux.tyco@...il.com>,
        Gabriel Fernandez <gabriel.fernandez@...com>,
        linux-arm-kernel@...ts.infradead.org
Subject: [PATCH 32/33] clk: lpc32xx: change round_rate() return logic

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <pure.logic@...us-software.ie>
Cc: Michael Turquette <mturquette@...libre.com>
Cc: Stephen Boyd <sboyd@...eaurora.org>
Cc: Vladimir Zapolskiy <vz@...ia.com>
Cc: Sylvain Lemieux <slemieux.tyco@...il.com>
Cc: Gabriel Fernandez <gabriel.fernandez@...com>
Cc: linux-clk@...r.kernel.org
Cc: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org
---
 drivers/clk/nxp/clk-lpc32xx.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 76c17f4..0e0d258 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -664,17 +664,17 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw,
 	 * USB divider, USB PLL N and M parameters.
 	 */
 	if (rate != 48000000)
-		return -EINVAL;
+		return 0;
 
 	/* USB divider clock */
 	usb_div_hw = clk_hw_get_parent_by_index(hw, 0);
 	if (!usb_div_hw)
-		return -EINVAL;
+		return 0;
 
 	/* Main oscillator clock */
 	osc_hw = clk_hw_get_parent_by_index(usb_div_hw, 0);
 	if (!osc_hw)
-		return -EINVAL;
+		return 0;
 	o = clk_hw_get_rate(osc_hw);	/* must be in range 1..20 MHz */
 
 	/* Check if valid USB divider and USB PLL parameters exists */
@@ -697,7 +697,7 @@ static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw,
 		}
 	}
 
-	return -EINVAL;
+	return 0;
 }
 
 #define LPC32XX_DEFINE_PLL_OPS(_name, _rc, _sr, _rr)			\
-- 
2.7.4