linux-kernel - [PATCH 25/33] clk: tegra: pll: change clk_pll_round

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Message-Id: <1514596392-22270-26-git-send-email-pure.logic@nexus-software.ie>
Date:   Sat, 30 Dec 2017 01:13:04 +0000
From:   Bryan O'Donoghue <pure.logic@...us-software.ie>
To:     mturquette@...libre.com, sboyd@...eaurora.org,
        linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org
Cc:     pure.logic@...us-software.ie,
        Peter De Schrijver <pdeschrijver@...dia.com>,
        Prashant Gaikwad <pgaikwad@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        linux-tegra@...r.kernel.org, Rhyland Klein <rklein@...dia.com>,
        Bill Huang <bilhuang@...dia.com>
Subject: [PATCH 25/33] clk: tegra: pll: change clk_pll_round_rate() return logic

This patch updates the round_rate() logic here to return zero instead of a
negative number on error.

In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.

Signed-off-by: Bryan O'Donoghue <pure.logic@...us-software.ie>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>
Cc: Prashant Gaikwad <pgaikwad@...dia.com>
Cc: Michael Turquette <mturquette@...libre.com>
Cc: Stephen Boyd <sboyd@...eaurora.org>
Cc: Thierry Reding <thierry.reding@...il.com>
Cc: Jonathan Hunter <jonathanh@...dia.com>
Cc: linux-clk@...r.kernel.org
Cc: linux-tegra@...r.kernel.org
Cc: linux-kernel@...r.kernel.org
Cc: Rhyland Klein <rklein@...dia.com>
Cc: Bill Huang <bilhuang@...dia.com>
---
 drivers/clk/tegra/clk-pll.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index b4a7d30..0a3edb0 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -839,7 +839,7 @@ static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 
 	if (_get_table_rate(hw, &cfg, rate, *prate) &&
 	    pll->params->calc_rate(hw, &cfg, rate, *prate))
-		return -EINVAL;
+		return 0;
 
 	return cfg.output_rate;
 }
-- 
2.7.4