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Message-Id: <1514978930-31341-7-git-send-email-mgautam@codeaurora.org>
Date: Wed, 3 Jan 2018 16:58:39 +0530
From: Manu Gautam <mgautam@...eaurora.org>
To: Kishon Vijay Abraham I <kishon@...com>
Cc: Felipe Balbi <balbi@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-usb@...r.kernel.org, Manu Gautam <mgautam@...eaurora.org>,
Vivek Gautam <vivek.gautam@...eaurora.org>,
Varadarajan Narayanan <varada@...eaurora.org>,
Wei Yongjun <weiyongjun1@...wei.com>,
Fengguang Wu <fengguang.wu@...el.com>,
linux-kernel@...r.kernel.org (open list:GENERIC PHY FRAMEWORK)
Subject: [PATCH v4 06/16] phy: qcom-qmp: Move SERDES/PCS START after PHY reset
Driver is currently performing PHY reset after starting
SERDES/PCS. As per hardware datasheet reset must be done
before starting PHY. Hence, update the sequence.
Signed-off-by: Manu Gautam <mgautam@...eaurora.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index ecff261..edb6bbe 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -896,12 +896,12 @@ static int qcom_qmp_phy_init(struct phy *phy)
if (cfg->has_pwrdn_delay)
usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
- /* start SerDes and Phy-Coding-Sublayer */
- qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
-
/* Pull PHY out of reset state */
qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
+ /* start SerDes and Phy-Coding-Sublayer */
+ qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
+
status = pcs + cfg->regs[QPHY_PCS_READY_STATUS];
mask = cfg->mask_pcs_ready;
--
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