linux-kernel - Re: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64

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Date:   Wed, 3 Jan 2018 16:01:11 +0200 (EET)
From:   Meelis Roos <mroos@...ux.ee>
To:     Thomas Gleixner <tglx@...utronix.de>
cc:     Borislav Petkov <bp@...en8.de>,
        Linux Kernel list <linux-kernel@...r.kernel.org>,
        x86@...nel.org, linux-edac@...r.kernel.org,
        Tom Lendacky <thomas.lendacky@....com>
Subject: Re: 4.15-rc6 PTI regression: L1 TLB mismatch MCE on Athlon64

> That's the entry area, which is mapped into kernel _AND_ user space. Now
> that's special because we switch CR3 while we are executing there.
> 
> And this one is:
> 
> 0xffffffff81e00000-0xffffffff82000000           2M     ro         PSE     GLB x  pmd
> 
> and the one we switch to is:
> 
> 0xffffffff81000000-0xffffffff82000000          16M     ro         PSE         x  pmd
> 
> Meelis, does the patch below fix it for you?

Yes, the MCE-s are gone with this patch on top of 4.15-rc6.

> 
> Thanks,
> 
> 	tglx
> 
> 8<-------------------
> 
> --- a/arch/x86/mm/pti.c
> +++ b/arch/x86/mm/pti.c
> @@ -367,7 +367,8 @@ static void __init pti_setup_espfix64(vo
>  static void __init pti_clone_entry_text(void)
>  {
>  	pti_clone_pmds((unsigned long) __entry_text_start,
> -			(unsigned long) __irqentry_text_end, _PAGE_RW);
> +			(unsigned long) __irqentry_text_end,
> +		       _PAGE_RW | _PAGE_GLOBAL);
>  }
>  
>  /*
> 

-- 
Meelis Roos (mroos@...ux.ee)