linux-kernel - Re: [PATCH v2 0/9] PCI: Add support to the Cadence PCIe controller

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Message-ID: <cfba420c-4b2e-c6d0-f708-336a2107f5b7@free-electrons.com>
Date:   Wed, 3 Jan 2018 22:22:17 +0100
From:   Cyrille Pitchen <cyrille.pitchen@...e-electrons.com>
To:     Kishon Vijay Abraham I <kishon@...com>, bhelgaas@...gle.com,
        lorenzo.pieralisi@....com, linux-pci@...r.kernel.org
Cc:     adouglas@...ence.com, stelford@...ence.com, dgary@...ence.com,
        kgopi@...ence.com, eandrews@...ence.com,
        thomas.petazzoni@...e-electrons.com, sureshp@...ence.com,
        nsekhar@...com, linux-kernel@...r.kernel.org, robh@...nel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v2 0/9] PCI: Add support to the Cadence PCIe controller

Hi Kishon,

Le 03/01/2018 à 10:14, Kishon Vijay Abraham I a écrit :
> Hi,
> 
> On Saturday 30 December 2017 02:23 AM, Cyrille Pitchen wrote:
>> Hi Kishon,
>>
>> Le 28/12/2017 à 14:00, Kishon Vijay Abraham I a écrit :
>>> Hi Cyrille,
>>>
>>> On Monday 18 December 2017 11:46 PM, Cyrille Pitchen wrote:
>>>> Hi all,
>>>>
>>>> this series of patches adds support to the Cadence PCIe controller.
>>>> It was tested on a ARM64 platform emulated by a Palladium running the
>>>> pci-next kernel.
>>>>
>>>> The host mode was tested with some PCIe devices connected to the Palladium
>>>> through a speed-bridge. Some of those devices were a USB host controller
>>>> and a SATA controller. The PCIe host controller was also tested with a
>>>> second controller configured in endpoint mode and connected back to back
>>>> to the first controller.
>>>>
>>>> The EndPoint Controller (EPC) driver of this series was tested with the
>>>> pci-epf-test.c EndPoint Function (EPF) driver and the pcitest userspace
>>>> program.
>>>
>>> Did you get to test multi function EP?
>>>
>>
>> No I didn't: I tested only with a single function to check for regression
>> but currently I'm not able to test with multiple functions.
>>
>> With devmem, I've tried to read then write the Physical Function Configuration
>> Register (offset 0x2c0 in the Local Management registers) to enable
>> functions other than function 0.
>>
>> This is the CDNS_PCIE_LM_EP_FUNC_CFG register that the pcie-cadence_ep.c
>> driver updates in cdns_pcie_ep_write_header() since v2 of the series.
>>
>> As written in the datasheet, BIT(0) is actually hard-wired to 1, hence
>> function 0 can't be disabled: that makes sense. However other function
>> enable bits were read as 0 whereas the datasheet claims they should be set
>> at power up. Besides, I can't set any of them with devmem.
>>
>> Actually, I have 2 slightly different datasheets, in the first one I should
>> have 4 functions but only 2 based on the second datasheet.
>>
>> Then I guess it's a design parameter used when synthesizing the controller.
>>
>> So I've asked Cadence whether I've missed or misunderstood something in the
>> datasheets or whether the IP they provided me with has a single function
>> for now. I'm waiting for their answers.
> 
> hmm.. It would be nice to have multi function tested since it would both
> validate multi function support of PCI EP core and the cadence multi-function
> itself.
>

I will work with Cadence so we try to make it work.

Best regards,

Cyrille

 
> Thanks
> Kishon
> 


-- 
Cyrille Pitchen, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com